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authorJason A. Donenfeld <Jason@zx2c4.com>2017-12-13 18:30:31 +0100
committerJason A. Donenfeld <Jason@zx2c4.com>2017-12-13 18:30:31 +0100
commit52004fdfdbe81112294ce060ee986f693e0c6b29 (patch)
tree34a3315f2bd425bde38029ae09fdf5bac0af8d57
parentwg-quick: dumber matching for default routes (diff)
downloadWireGuard-master.zip
WireGuard-master.tar.xz
crypto: compile on UMLHEADmaster
We basically just don't use FPU in UML.
-rw-r--r--src/crypto/blake2s.c2
-rw-r--r--src/crypto/chacha20poly1305.c2
-rw-r--r--src/crypto/chacha20poly1305.h4
-rw-r--r--src/crypto/curve25519.c2
4 files changed, 8 insertions, 2 deletions
diff --git a/src/crypto/blake2s.c b/src/crypto/blake2s.c
index c0b95be..5c3f8f0 100644
--- a/src/crypto/blake2s.c
+++ b/src/crypto/blake2s.c
@@ -119,10 +119,12 @@ static bool blake2s_use_avx __read_mostly;
static bool blake2s_use_avx512 __read_mostly;
void __init blake2s_fpu_init(void)
{
+#ifndef CONFIG_UML
blake2s_use_avx = boot_cpu_has(X86_FEATURE_AVX) && cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL);
#ifndef COMPAT_CANNOT_USE_AVX512
blake2s_use_avx512 = boot_cpu_has(X86_FEATURE_AVX) && boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX512F) && boot_cpu_has(X86_FEATURE_AVX512VL) && cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM | XFEATURE_MASK_AVX512, NULL);
#endif
+#endif
}
#ifdef CONFIG_AS_AVX
asmlinkage void blake2s_compress_avx(struct blake2s_state *state, const u8 *block, size_t nblocks, u32 inc);
diff --git a/src/crypto/chacha20poly1305.c b/src/crypto/chacha20poly1305.c
index 4173973..6be96f6 100644
--- a/src/crypto/chacha20poly1305.c
+++ b/src/crypto/chacha20poly1305.c
@@ -46,6 +46,7 @@ static bool chacha20poly1305_use_avx512vl __read_mostly;
void __init chacha20poly1305_fpu_init(void)
{
+#ifndef CONFIG_UML
chacha20poly1305_use_ssse3 = boot_cpu_has(X86_FEATURE_SSSE3);
chacha20poly1305_use_avx = boot_cpu_has(X86_FEATURE_AVX) &&
cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL);
@@ -58,6 +59,7 @@ void __init chacha20poly1305_fpu_init(void)
chacha20poly1305_use_avx512vl = boot_cpu_has(X86_FEATURE_AVX) && boot_cpu_has(X86_FEATURE_AVX2) && boot_cpu_has(X86_FEATURE_AVX512F) && boot_cpu_has(X86_FEATURE_AVX512VL) &&
cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM | XFEATURE_MASK_AVX512, NULL);
#endif
+#endif
}
#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64)
asmlinkage void poly1305_init_arm(void *ctx, const u8 key[16]);
diff --git a/src/crypto/chacha20poly1305.h b/src/crypto/chacha20poly1305.h
index 1e54594..8e7b886 100644
--- a/src/crypto/chacha20poly1305.h
+++ b/src/crypto/chacha20poly1305.h
@@ -58,7 +58,7 @@ bool __must_check xchacha20poly1305_decrypt(u8 *dst, const u8 *src, const size_t
static inline bool chacha20poly1305_init_simd(void)
{
bool have_simd = false;
-#if defined(CONFIG_X86_64)
+#if defined(CONFIG_X86_64) && !defined(CONFIG_UML)
have_simd = irq_fpu_usable();
if (have_simd)
kernel_fpu_begin();
@@ -76,7 +76,7 @@ static inline bool chacha20poly1305_init_simd(void)
static inline void chacha20poly1305_deinit_simd(bool was_on)
{
-#if defined(CONFIG_X86_64)
+#if defined(CONFIG_X86_64) && !defined(CONFIG_UML)
if (was_on)
kernel_fpu_end();
#elif IS_ENABLED(CONFIG_KERNEL_MODE_NEON)
diff --git a/src/crypto/curve25519.c b/src/crypto/curve25519.c
index adf6a0b..1daebfe 100644
--- a/src/crypto/curve25519.c
+++ b/src/crypto/curve25519.c
@@ -33,7 +33,9 @@ static __always_inline void normalize_secret(u8 secret[CURVE25519_POINT_SIZE])
static bool curve25519_use_avx __read_mostly;
void __init curve25519_fpu_init(void)
{
+#ifndef CONFIG_UML
curve25519_use_avx = boot_cpu_has(X86_FEATURE_AVX) && cpu_has_xfeatures(XFEATURE_MASK_SSE | XFEATURE_MASK_YMM, NULL);
+#endif
}
typedef u64 fe[10];