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<title>glibc/sysdeps/x86/include, branch master</title>
<subtitle>Fork of glibc for development</subtitle>
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<updated>2024-07-16T09:20:18Z</updated>
<entry>
<title>x86: Disable non-temporal memset on Skylake Server</title>
<updated>2024-07-16T09:20:18Z</updated>
<author>
<name>Noah Goldstein</name>
<email>goldstein.w.n@gmail.com</email>
</author>
<published>2024-07-15T08:19:17Z</published>
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<id>urn:sha1:5bcf6265f215326d14dfacdce8532792c2c7f8f8</id>
<content type='text'>
The original commit enabling non-temporal memset on Skylake Server had
erroneous benchmarks (actually done on ICX).

Further benchmarks indicate non-temporal stores may in fact by a
regression on Skylake Server.

This commit may be over-cautious in some cases, but should avoid any
regressions for 2.40.

Tested using qemu on all x86_64 cpu arch supported by both qemu +
GLIBC.

Reviewed-by: DJ Delorie &lt;dj@redhat.com&gt;
Reviewed-by: H.J. Lu &lt;hjl.tools@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86: Add seperate non-temporal tunable for memset</title>
<updated>2024-05-30T17:36:09Z</updated>
<author>
<name>Noah Goldstein</name>
<email>goldstein.w.n@gmail.com</email>
</author>
<published>2024-05-24T17:38:51Z</published>
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<id>urn:sha1:46b5e98ef6f1b9f4b53851f152ecb8209064b26c</id>
<content type='text'>
The tuning for non-temporal stores for memset vs memcpy is not always
the same. This includes both the exact value and whether non-temporal
stores are profitable at all for a given arch.

This patch add `x86_memset_non_temporal_threshold`. Currently we
disable non-temporal stores for non Intel vendors as the only
benchmarks showing its benefit have been on Intel hardware.
Reviewed-by: H.J. Lu &lt;hjl.tools@gmail.com&gt;
</content>
</entry>
<entry>
<title>x86-64: Update _dl_tlsdesc_dynamic to preserve AMX registers</title>
<updated>2024-02-29T12:30:01Z</updated>
<author>
<name>H.J. Lu</name>
<email>hjl.tools@gmail.com</email>
</author>
<published>2024-02-28T20:08:03Z</published>
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<id>urn:sha1:9b7091415af47082664717210ac49d51551456ab</id>
<content type='text'>
_dl_tlsdesc_dynamic should also preserve AMX registers which are
caller-saved.  Add X86_XSTATE_TILECFG_ID and X86_XSTATE_TILEDATA_ID
to x86-64 TLSDESC_CALL_STATE_SAVE_MASK.  Compute the AMX state size
and save it in xsave_state_full_size which is only used by
_dl_tlsdesc_dynamic_xsave and _dl_tlsdesc_dynamic_xsavec.  This fixes
the AMX part of BZ #31372.  Tested on AMX processor.

AMX test is enabled only for compilers with the fix for

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114098

GCC 14 and GCC 11/12/13 branches have the bug fix.
Reviewed-by: Sunil K Pandey &lt;skpgkp2@gmail.com&gt;
</content>
</entry>
<entry>
<title>Update copyright dates with scripts/update-copyrights</title>
<updated>2024-01-01T18:53:40Z</updated>
<author>
<name>Paul Eggert</name>
<email>eggert@cs.ucla.edu</email>
</author>
<published>2024-01-01T18:12:26Z</published>
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<id>urn:sha1:dff8da6b3e89b986bb7f6b1ec18cf65d5972e307</id>
<content type='text'>
</content>
</entry>
<entry>
<title>x86/cet: Enable shadow stack during startup</title>
<updated>2024-01-01T13:22:48Z</updated>
<author>
<name>H.J. Lu</name>
<email>hjl.tools@gmail.com</email>
</author>
<published>2023-12-29T16:43:51Z</published>
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<id>urn:sha1:541641a3de8d89464151bd879552755e882c832e</id>
<content type='text'>
Previously, CET was enabled by kernel before passing control to user
space and the startup code must disable CET if applications or shared
libraries aren't CET enabled.  Since the current kernel only supports
shadow stack and won't enable shadow stack before passing control to
user space, we need to enable shadow stack during startup if the
application and all shared library are shadow stack enabled.  There
is no need to disable shadow stack at startup.  Shadow stack can only
be enabled in a function which will never return.  Otherwise, shadow
stack will underflow at the function return.

1. GL(dl_x86_feature_1) is set to the CET features which are supported
by the processor and are not disabled by the tunable.  Only non-zero
features in GL(dl_x86_feature_1) should be enabled.  After enabling
shadow stack with ARCH_SHSTK_ENABLE, ARCH_SHSTK_STATUS is used to check
if shadow stack is really enabled.
2. Use ARCH_SHSTK_ENABLE in RTLD_START in dynamic executable.  It is
safe since RTLD_START never returns.
3. Call arch_prctl (ARCH_SHSTK_ENABLE) from ARCH_SETUP_TLS in static
executable.  Since the start function using ARCH_SETUP_TLS never returns,
it is safe to enable shadow stack in ARCH_SETUP_TLS.
</content>
</entry>
<entry>
<title>x86: Add support for AVX10 preset and vec size in cpu-features</title>
<updated>2023-09-29T19:18:42Z</updated>
<author>
<name>Noah Goldstein</name>
<email>goldstein.w.n@gmail.com</email>
</author>
<published>2023-09-20T20:44:50Z</published>
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<id>urn:sha1:d90b43a4ed475dac5b0cd6e01ceb35c7b0f7f2ff</id>
<content type='text'>
This commit add support for the new AVX10 cpu features:
https://cdrdv2-public.intel.com/784267/355989-intel-avx10-spec.pdf

We add checks for:
    - `AVX10`: Check if AVX10 is present.
    - `AVX10_{X,Y,Z}MM`: Check if a given vec class has AVX10 support.

`make check` passes and cpuid output was checked against GNR/DMR on an
emulator.
</content>
</entry>
<entry>
<title>&lt;sys/platform/x86.h&gt;: Add APX support</title>
<updated>2023-07-27T15:42:32Z</updated>
<author>
<name>H.J. Lu</name>
<email>hjl.tools@gmail.com</email>
</author>
<published>2023-07-26T15:20:16Z</published>
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<id>urn:sha1:1547d6a64f4b981a06fd46ee446425a32558f2d0</id>
<content type='text'>
Add support for Intel Advanced Performance Extensions:

https://www.intel.com/content/www/us/en/developer/articles/technical/advanced-performance-extensions-apx.html

to &lt;sys/platform/x86.h&gt;.
</content>
</entry>
<entry>
<title>x86: Make the divisor in setting `non_temporal_threshold` cpu specific</title>
<updated>2023-06-12T16:33:39Z</updated>
<author>
<name>Noah Goldstein</name>
<email>goldstein.w.n@gmail.com</email>
</author>
<published>2023-06-07T18:18:03Z</published>
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<id>urn:sha1:180897c161a171d8ef0faee1c6c9fd6b57d8b13b</id>
<content type='text'>
Different systems prefer a different divisors.

From benchmarks[1] so far the following divisors have been found:
    ICX     : 2
    SKX     : 2
    BWD     : 8

For Intel, we are generalizing that BWD and older prefers 8 as a
divisor, and SKL and newer prefers 2. This number can be further tuned
as benchmarks are run.

[1]: https://github.com/goldsteinn/memcpy-nt-benchmarks
Reviewed-by: DJ Delorie &lt;dj@redhat.com&gt;
</content>
</entry>
<entry>
<title>&lt;sys/platform/x86.h&gt;: Add PREFETCHI support</title>
<updated>2023-04-05T21:46:10Z</updated>
<author>
<name>H.J. Lu</name>
<email>hjl.tools@gmail.com</email>
</author>
<published>2023-04-05T16:21:44Z</published>
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<id>urn:sha1:81a3cc956ef4e324c83419fa6d7a559d6e762cd7</id>
<content type='text'>
Add PREFETCHI support to &lt;sys/platform/x86.h&gt;.
Reviewed-by: Noah Goldstein &lt;goldstein.w.n@gmail.com&gt;
</content>
</entry>
<entry>
<title>&lt;sys/platform/x86.h&gt;: Add AMX-COMPLEX support</title>
<updated>2023-04-05T21:46:10Z</updated>
<author>
<name>H.J. Lu</name>
<email>hjl.tools@gmail.com</email>
</author>
<published>2023-04-05T16:21:43Z</published>
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<id>urn:sha1:b05521c916790dbaeb953fca7b979a889d868db2</id>
<content type='text'>
Add AMX-COMPLEX support to &lt;sys/platform/x86.h&gt;.
Reviewed-by: Noah Goldstein &lt;goldstein.w.n@gmail.com&gt;
</content>
</entry>
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