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author | 2019-08-20 15:57:35 -0500 | |
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committer | 2019-08-28 13:53:09 -0500 | |
commit | 0b3c9e57a41d9f7c26fb6aa45b99f671bef9c7e0 (patch) | |
tree | 17e86cc4b838006df6a22738a4d48f6e8f2e51e8 /scripts/test_printers_exceptions.py | |
parent | [powerpc] fesetenv: optimize FPSCR access (diff) | |
download | glibc-0b3c9e57a41d9f7c26fb6aa45b99f671bef9c7e0.tar.xz glibc-0b3c9e57a41d9f7c26fb6aa45b99f671bef9c7e0.zip |
[powerpc] fegetenv_status: simplify instruction generation
fegetenv_status() wants to use the lighter weight instruction 'mffsl'
for reading the Floating-Point Status and Control Register (FPSCR).
It currently will use it directly if compiled '-mcpu=power9', and will
perform a runtime check (cpu_supports("arch_3_00")) otherwise.
Nicely, it turns out that the 'mffsl' instruction will decode to
'mffs' on architectures older than "arch_3_00" because the additional
bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset
of 'mffsl'.
So, just generate 'mffsl'.
Diffstat (limited to 'scripts/test_printers_exceptions.py')
0 files changed, 0 insertions, 0 deletions