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| author |   Feifei Wang <wangfeifei@hygon.cn> | 2024-08-19 14:57:54 +0800 |
|---|---|---|
| committer |   H.J. Lu <hjl.tools@gmail.com> | 2024-08-26 10:01:58 -0700 |
| commit | d14aecbffc032c97d86fdbfdcb7991d1a55e8399 (patch) | |
| tree | 0249dafb86d71c376eb1790ecbcd53340c5bd8eb /sysdeps/unix/sysv/linux/readdir_r.c | |
| parent | x86: Add new architecture type for Hygon processors (diff) | |
| download | glibc-d14aecbffc032c97d86fdbfdcb7991d1a55e8399.tar.xz glibc-d14aecbffc032c97d86fdbfdcb7991d1a55e8399.zip | |
x86: Add cache information support for Hygon processors
Add hygon branch in dl_init_cacheinfo function to initialize
cache size variables for hygon processors. In the meanwhile,
add handle_hygon() function to get cache information.
Signed-off-by: Feifei Wang <wangfeifei@hygon.cn>
Reviewed-by: Jing Li <lijing@hygon.cn>
Reviewed-by: H.J. Lu <hjl.tools@gmail.com>
Diffstat (limited to '')
0 files changed, 0 insertions, 0 deletions