linux-dev/Documentation/devicetree/bindings/arm/msm, branch master

dt-bindings: Fix typo in comment

2022-07-21T19:14:27Z

Fix typo in the comment Signed-off-by: Slark Xiao Reviewed-by: Krzysztof Kozlowski Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220721011746.19663-1-slark_xiao@163.com

dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles

2022-05-04T16:39:40Z

Add compatibles for the SC8180X and SC8280XP platforms to the existing LLCC binding. Acked-by: Krzysztof Kozlowski Signed-off-by: Bjorn Andersson Acked-by: Rob Herring Link: https://lore.kernel.org/r/20220502215406.612967-2-bjorn.andersson@linaro.org

RISC-V CPU Idle Support

2022-03-30T23:17:54Z

This series adds RISC-V CPU Idle support using SBI HSM suspend function. The RISC-V SBI CPU idle driver added by this series is highly inspired from the ARM PSCI CPU idle driver. Special thanks Sandeep Tripathy for providing early feeback on SBI HSM support in all above projects (RISC-V SBI specification, OpenSBI, and Linux RISC-V). * palmer/riscv-idle: RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine dt-bindings: Add common bindings for ARM and RISC-V idle states cpuidle: Add RISC-V SBI CPU idle driver cpuidle: Factor-out power domain related code from PSCI domain driver RISC-V: Add SBI HSM suspend related defines RISC-V: Add arch functions for non-retentive suspend entry/exit RISC-V: Rename relocate() and make it global RISC-V: Enable CPU_IDLE drivers

dt-bindings: Add common bindings for ARM and RISC-V idle states

2022-03-10T17:29:56Z

The RISC-V CPU idle states will be described in under the /cpus/idle-states DT node in the same way as ARM CPU idle states. This patch adds common bindings documentation for both ARM and RISC-V idle states. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Rob Herring Reviewed-by: Guo Ren Signed-off-by: Palmer Dabbelt

dt-bindings: arm: msm: Add LLCC compatible for SM8450

2022-02-11T00:29:33Z

Add LLCC compatible for SM8450 SoC. Cc: Rob Herring Signed-off-by: Sai Prakash Ranjan Reviewed-by: Krzysztof Kozlowski Tested-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/f5235371f07ac0ce367c6ea84ed49937fb751a07.1643355594.git.quic_saipraka@quicinc.com

dt-bindings: arm: msm: Add LLCC compatible for SM8350

2022-02-11T00:29:33Z

Add LLCC compatible for SM8350 SoC. Cc: Rob Herring Signed-off-by: Sai Prakash Ranjan Reviewed-by: Krzysztof Kozlowski Tested-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/e3d200eb06949f7e216b7f82f5811b7addb7fdc8.1643355594.git.quic_saipraka@quicinc.com

dt-bindings: arm: msm: Don't mark LLCC interrupt as required

2021-12-21T01:10:11Z

Newer SoCs like SM6350 or SM8250 don't provide an interrupt for LLCC. Signed-off-by: Luca Weiss Acked-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082614.22651-9-luca.weiss@fairphone.com

dt-bindings: arm: msm: Add LLCC for SM6350

2021-12-21T01:10:11Z

Add LLCC compatible for SM6350 SoC. Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Konrad Dybcio Acked-by: Rob Herring Signed-off-by: Luca Weiss Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211213082614.22651-2-luca.weiss@fairphone.com

dt-bindings: arm: msm: Add SAW2 for MSM8226

2021-06-16T18:03:01Z

Add the dt-binding compatible in the SPM AVS Wrapper 2 (SAW2) for the MSM8226 SoC platform. Acked-by: Rob Herring Signed-off-by: Bartosz Dudziak Signed-off-by: Daniel Lezcano Link: https://lore.kernel.org/r/20210612205335.9730-2-bartosz.dudziak@snejp.pl

dt-bindings: arm: msm: Add LLCC for SC7280

2021-03-12T02:22:20Z

Add LLCC compatible for SC7280 SoC. Acked-by: Rob Herring Reviewed-by: Stephen Boyd Signed-off-by: Sai Prakash Ranjan Link: https://lore.kernel.org/r/f3b32d437d7c1165a74ceec2cd52ff56b496e5a3.1614244789.git.saiprakash.ranjan@codeaurora.org Signed-off-by: Bjorn Andersson