linux-dev/Documentation/devicetree/bindings/clock/sunxi.txt, branch master

dt-bindings: clocks: Convert Allwinner legacy clocks to schemas

2019-12-24T21:17:52Z

The Allwinner SoCs have a legacy set of bindings (and a framework to support it in Linux) for their clock controllers. Now that we have the DT validation in place, let's split into separate file and convert the device tree bindings for those clocks to schemas, and mark them all as deprecated. Signed-off-by: Maxime Ripard Signed-off-by: Rob Herring

dt-bindings: Remove leading zeros from bindings notation

2017-11-09T23:05:05Z

Improve the binding example by removing all the leading zeros to fix the following dtc warnings: Warning (unit_address_format): Node /XXX unit name should not have leading 0s Converted using the following command: perl -p -i -e 's/\@0+([0-9a-f])/\@$1/g' `find ./Documentation/devicetree/bindings "*.txt"` Some unnecessary changes were manually fixed. Signed-off-by: Marco Franchi Signed-off-by: Rob Herring

clk: sunxi: Add display and TCON0 clocks driver

2016-05-12T21:47:52Z

The A10 SoCs and its relatives has a special clock controller to drive the display engines (both frontend and backend), that have a lot in common with the clock to drive the first TCON channel. Add a driver to support both. Signed-off-by: Maxime Ripard Acked-by: Rob Herring [sboyd@codeaurora.org: Silence variable sized array warning] Signed-off-by: Stephen Boyd

clk: sunxi: Add TCON channel1 clock

2016-04-21T22:29:24Z

The TCON is a controller generating the timings to output videos signals, acting like both a CRTC and an encoder. It has two channels depending on the output, each channel being driven by its own clock (and own clock controller). Add a driver for the channel 1 clock. Signed-off-by: Maxime Ripard Acked-by: Rob Herring Acked-by: Stephen Boyd

clk: sunxi: Add PLL3 clock

2016-04-21T22:29:23Z

The A10 SoCs and relatives have a PLL controller to drive the PLL3 and PLL7, clocked from a 3MHz oscillator, that drives the display related clocks (GPU, display engine, TCON, etc.) Add a driver for it. Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Acked-by: Stephen Boyd Signed-off-by: Maxime Ripard

dt-bindings: clk: sun5i: add DRAM gates compatible

2016-04-21T22:29:23Z

The Allwinner SoCs have a gate controller to gate the access to the DRAM clock to the some devices that need to access the DRAM directly (mostly display / image related IPs). Use a simple gates driver to support the one found in the A13 / R8 SoCs. Signed-off-by: Maxime Ripard Acked-by: Chen-Yu Tsai Acked-by: Rob Herring Acked-by: Stephen Boyd Signed-off-by: Maxime Ripard

clk: sunxi: Add sun6i/8i display support

2016-04-21T22:29:22Z

Add the clock type which is used by the sun6i/8i families for video display. Signed-off-by: Jean-Francois Moine Acked-by: Rob Herring Signed-off-by: Maxime Ripard

clk: sunxi: Add apb0 gates for H3

2016-02-25T19:30:32Z

This patch adds support for APB0 in H3. It seems to be compatible with earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR, etc). Since this gates behave just like any Allwinner clock gate, add a generic compatible that can be reused if we don't have any clock to protect. Signed-off-by: Krzysztof Adamski [Maxime: Removed the H3 compatible from the simple-gates driver, reworked the commit log a bit] Signed-off-by: Maxime Ripard

clk: sunxi: add bus gates for A83T

2016-02-02T13:14:24Z

A83T has similar bus gates that of H3, including single gating register has different clock parent. As per H3 and A83T datasheet, usbhost is under AHB2. However,below shows allwinner source code assignment: bits: 26 (ehci0), 27 (ehci1), 29 (ohci0) => AHB1 for A83T. bits: 26 (ehci0), 27 (ehci1) => AHB1 for H3 bits 29, 30, 31(ohci0,1,2) => AHB2 for H3. until, this confusion is cleared keep it H3 way. Signed-off-by: Vishnu Patekar Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard

clk: sunxi: Add apb0 gates for A83T

2016-02-02T13:11:46Z

APB0 is part of PRCM, and is compatible with earlier SOCs. apb0 gates controls R_PIO, R_UART, R_RSB, etc clocks. This patch adds support for APB0 gates for A83T. Signed-off-by: Vishnu Patekar Acked-by: Rob Herring Acked-by: Chen-Yu Tsai Signed-off-by: Maxime Ripard