linux-dev/Documentation/devicetree/bindings/display/tegra, branch linus/master

dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D

2021-12-17T13:58:06Z

Memory Client should be blocked before hardware reset is asserted in order to prevent memory corruption and hanging of memory controller. Document Memory Client resets of Host1x, GR2D and GR3D hardware units. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

dt-bindings: host1x: Document OPP and power domain properties

2021-12-17T13:58:05Z

Document new DVFS OPP table and power domain properties of the Host1x bus and devices sitting on the bus. Reviewed-by: Rob Herring Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes

2021-01-04T12:02:44Z

Tegra VI/CSI hardware don't have native 8 lane CSI RX port. But x8 capture can be supported by using consecutive x4 ports simultaneously with HDMI-to-CSI bridges where source image is split on to two x4 ports. This patch updates dt-bindings for csi endpoint data-lane property with maximum of 8 lanes. Acked-by: Rob Herring Acked-by: Sakari Ailus Signed-off-by: Sowjanya Komatineni Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

dt-bindings: host1x: Document new interconnect properties

2020-11-06T18:37:20Z

Most of Host1x devices have at least one memory client. These clients are directly connected to the memory controller. The new interconnect properties represent the memory client's connection to the memory controller. Signed-off-by: Dmitry Osipenko Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20201104164923.21238-17-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski

media: dt-bindings: tegra: Update VI and CSI bindings with port info

2020-08-28T13:10:10Z

Update VI and CSI bindings to add port and endpoint nodes as per media video-interfaces DT binding document. Acked-by: Rob Herring Signed-off-by: Sowjanya Komatineni Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab

dt-bindings: tegra: Add VI and CSI bindings

2020-05-12T20:47:15Z

Tegra contains VI controller which can support up to 6 MIPI CSI camera sensors. Each Tegra CSI port from CSI unit can be one-to-one mapper to VI channel and can capture from an external camera sensor or from built-in test pattern generator. This patch adds dt-bindings for Tegra VI and CSI. Acked-by: Thierry Reding Reviewed-by: Rob Herring Signed-off-by: Sowjanya Komatineni Signed-off-by: Thierry Reding

dt-bindings: display: tegra: Support SOR crossbar configuration

2019-02-07T17:29:01Z

The SOR has a crossbar that can map each lane of the SOR to each of the SOR pads. The mapping is usually the same across designs for a specific SoC generation, but every now and then there's a design that doesn't. Allow the crossbar configuration to be specified in device tree to make it possible to support these designs. Signed-off-by: Thierry Reding

dt-bindings: display: tegra: Update SOR for Tegra186

2017-12-13T12:42:04Z

Update the SOR bindings for Tegra186, in which a new property is required to identify the instance of the SOR interface and the clock tree has slightly changed as well. Signed-off-by: Thierry Reding

dt-bindings: host1x: Add Tegra186 information

2017-10-20T12:19:51Z

Add the Tegra186-specific hypervisor-related register range properties. Signed-off-by: Mikko Perttunen Acked-by: Rob Herring Signed-off-by: Thierry Reding

dt-bindings: Add bindings for the Tegra VIC

2017-04-05T16:11:48Z

The VIC (Video Image Compositor) is a Host1x client unit that can do various 2D composition and transform operations. Signed-off-by: Mikko Perttunen Signed-off-by: Thierry Reding