Linux kernel development work - see feature branches https://git.zx2c4.com/linux-dev/atom/Documentation/devicetree/bindings/iommu?h=linus%2Fmaster 2022-06-06T14:07:30Z 2022-06-06T14:07:30Z Oleksandr Tyshchenko oleksandr_tyshchenko@epam.com 2022-06-02T19:23:50Z urn:sha1:add413a1d966d8458571a2571881903d234a9f8e The main purpose of this binding is to communicate Xen specific information using generic IOMMU device tree bindings (which is a good fit here) rather than introducing a custom property. Introduce Xen specific IOMMU for the virtualized device (e.g. virtio) to be used by Xen grant DMA-mapping layer in the subsequent commit. The reference to Xen specific IOMMU node using "iommus" property indicates that Xen grant mappings need to be enabled for the device, and it specifies the ID of the domain where the corresponding backend resides. The domid (domain ID) is used as an argument to the Xen grant mapping APIs. This is needed for the option to restrict memory access using Xen grant mappings to work which primary goal is to enable using virtio devices in Xen guests. Signed-off-by: Oleksandr Tyshchenko <oleksandr_tyshchenko@epam.com> Reviewed-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1654197833-25362-6-git-send-email-olekstysh@gmail.com Signed-off-by: Juergen Gross <jgross@suse.com> 2022-05-31T16:56:54Z Linus Torvalds torvalds@linux-foundation.org 2022-05-31T16:56:54Z urn:sha1:e1cbc3b96a9974746b2a80c3a6c8a0f7eff7b1b5 Pull iommu updates from Joerg Roedel: - Intel VT-d driver updates: - Domain force snooping improvement. - Cleanups, no intentional functional changes. - ARM SMMU driver updates: - Add new Qualcomm device-tree compatible strings - Add new Nvidia device-tree compatible string for Tegra234 - Fix UAF in SMMUv3 shared virtual addressing code - Force identity-mapped domains for users of ye olde SMMU legacy binding - Minor cleanups - Fix a BUG_ON in the vfio_iommu_group_notifier: - Groundwork for upcoming iommufd framework - Introduction of DMA ownership so that an entire IOMMU group is either controlled by the kernel or by user-space - MT8195 and MT8186 support in the Mediatek IOMMU driver - Make forcing of cache-coherent DMA more coherent between IOMMU drivers - Fixes for thunderbolt device DMA protection - Various smaller fixes and cleanups * tag 'iommu-updates-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (88 commits) iommu/amd: Increase timeout waiting for GA log enablement iommu/s390: Tolerate repeat attach_dev calls iommu/vt-d: Remove hard coding PGSNP bit in PASID entries iommu/vt-d: Remove domain_update_iommu_snooping() iommu/vt-d: Check domain force_snooping against attached devices iommu/vt-d: Block force-snoop domain attaching if no SC support iommu/vt-d: Size Page Request Queue to avoid overflow condition iommu/vt-d: Fold dmar_insert_one_dev_info() into its caller iommu/vt-d: Change return type of dmar_insert_one_dev_info() iommu/vt-d: Remove unneeded validity check on dev iommu/dma: Explicitly sort PCI DMA windows iommu/dma: Fix iova map result check bug iommu/mediatek: Fix NULL pointer dereference when printing dev_name iommu: iommu_group_claim_dma_owner() must always assign a domain iommu/arm-smmu: Force identity domains for legacy binding iommu/arm-smmu: Support Tegra234 SMMU dt-bindings: arm-smmu: Add compatible for Tegra234 SOC dt-bindings: arm-smmu: Document nvidia,memory-controller property iommu/arm-smmu-qcom: Add SC8280XP support dt-bindings: arm-smmu: Add compatible for Qualcomm SC8280XP ... 2022-05-26T17:32:47Z Linus Torvalds torvalds@linux-foundation.org 2022-05-26T17:32:47Z urn:sha1:cc3c470ae4ad758b8ddad825ab199f7eaa8b0a9e Pull ARM driver updates from Arnd Bergmann: "There are minor updates to SoC specific drivers for chips by Rockchip, Samsung, NVIDIA, TI, NXP, i.MX, Qualcomm, and Broadcom. Noteworthy driver changes include: - Several conversions of DT bindings to yaml format. - Renesas adds driver support for R-Car V4H, RZ/V2M and RZ/G2UL SoCs. - Qualcomm adds a bus driver for the SSC (Snapdragon Sensor Core), and support for more chips in the RPMh power domains and the soc-id. - NXP has a new driver for the HDMI blk-ctrl on i.MX8MP. - Apple M1 gains support for the on-chip NVMe controller, making it possible to finally use the internal disks. This also includes SoC drivers for their RTKit IPC and for the SART DMA address filter. For other subsystems that merge their drivers through the SoC tree, we have - Firmware drivers for the ARM firmware stack including TEE, OP-TEE, SCMI and FF-A get a number of smaller updates and cleanups. OP-TEE now has a cache for firmware argument structures as an optimization, and SCMI now supports the 3.1 version of the specification. - Reset controller updates to Amlogic, ASpeed, Renesas and ACPI drivers - Memory controller updates for Tegra, and a few updates for other platforms" * tag 'arm-drivers-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (159 commits) memory: tegra: Add MC error logging on Tegra186 onward memory: tegra: Add memory controller channels support memory: tegra: Add APE memory clients for Tegra234 memory: tegra: Add Tegra234 support nvme-apple: fix sparse endianess warnings soc/tegra: pmc: Document core domain fields soc: qcom: pdr: use static for servreg_* variables soc: imx: fix semicolon.cocci warnings soc: renesas: R-Car V3U is R-Car Gen4 soc: imx: add i.MX8MP HDMI blk-ctrl soc: imx: imx8m-blk-ctrl: Add i.MX8MP media blk-ctrl soc: imx: add i.MX8MP HSIO blk-ctrl soc: imx: imx8m-blk-ctrl: set power device name soc: qcom: llcc: Add sc8180x and sc8280xp configurations dt-bindings: arm: msm: Add sc8180x and sc8280xp LLCC compatibles soc/tegra: pmc: Select REGMAP dt-bindings: reset: st,sti-powerdown: Convert to yaml dt-bindings: reset: st,sti-picophyreset: Convert to yaml dt-bindings: reset: socfpga: Convert to yaml dt-bindings: reset: snps,axs10x-reset: Convert to yaml ... 2022-05-20T10:27:17Z Joerg Roedel jroedel@suse.de 2022-05-20T10:27:17Z urn:sha1:b0dacee202efbf1a5d9f5cdfd82049e8b5b085d2 2022-05-09T16:03:48Z Andre Przywara andre.przywara@arm.com 2022-05-06T14:05:23Z urn:sha1:e4783856a2e8e41c679fd818afc912904d4088ba The Page Request Interface (PRI) is an optional PCIe feature. As such, a SMMU would not need to handle it if the PCIe host bridge or the SMMU itself do not implement it. Also an SMMU could be connected to a platform device, without any PRI functionality whatsoever. In all cases there would be no SMMU PRI queue interrupt to be wired up to an interrupt controller. At the moment, with the "eventq,gerror,priq,cmdq-sync" order, we would need to sacrifice the command queue sync interrupt as well, which might not be desired. Relax the binding to allow specifying certain useful combinations of wired interrupts, for instance just the "gerror" interrupt, or omitting both "pri" and "cmdq-sync". Signed-off-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20220506140533.3566431-2-andre.przywara@arm.com 2022-05-06T15:29:27Z Thierry Reding treding@nvidia.com 2022-04-29T08:22:42Z urn:sha1:95d5aeabda00baaccb2be262511adac74255dd7c The NVIDIA Tegra234 SoC comes with one single-instance ARM SMMU used by isochronous memory clients and two dual-instance ARM SMMUs used by non- isochronous memory clients. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220429082243.496000-3-thierry.reding@gmail.com Signed-off-by: Will Deacon <will@kernel.org> 2022-05-06T15:29:27Z Thierry Reding treding@nvidia.com 2022-04-29T08:22:41Z urn:sha1:c02bda09f91a340bc9fae4e236ce3e3ec6b1c9ff On NVIDIA SoC's the ARM SMMU needs to interact with the memory controller in order to map memory clients to the corresponding stream IDs. Document how the nvidia,memory-controller property can be used to achieve this. Note that this is a backwards-incompatible change that is, however, necessary to ensure correctness. Without the new property, most of the devices would still work but it is not guaranteed that all will. Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Will Deacon <will@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com> Link: https://lore.kernel.org/r/20220429082243.496000-2-thierry.reding@gmail.com Signed-off-by: Will Deacon <will@kernel.org> 2022-05-06T15:27:59Z Bjorn Andersson bjorn.andersson@linaro.org 2022-05-03T16:34:28Z urn:sha1:38db6b41b2f499c3a6e068f7796a2dd050b24166 Add compatible for the Qualcomm SC8280XP platform to the ARM SMMU DeviceTree binding. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20220503163429.960998-2-bjorn.andersson@linaro.org Signed-off-by: Will Deacon <will@kernel.org> 2022-05-06T15:22:05Z Rohit Agarwal quic_rohiagar@quicinc.com 2022-04-11T09:50:12Z urn:sha1:5a4eb91634711aa6278d0f5b3d33c3ea63397639 Add devicetree binding for Qualcomm SDX65 SMMU. Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/1649670615-21268-5-git-send-email-quic_rohiagar@quicinc.com Signed-off-by: Will Deacon <will@kernel.org> 2022-05-04T08:39:38Z Yong Wu yong.wu@mediatek.com 2022-05-03T07:13:54Z urn:sha1:2d555a3844142b9e0f876925a8475cc830cd472a Add mt8186 iommu binding. "-mm" means the iommu is for Multimedia. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20220503071427.2285-4-yong.wu@mediatek.com Signed-off-by: Joerg Roedel <jroedel@suse.de>