linux-dev/arch/arc/plat-sim, branch master

ARC: merge HAPS-HS with nSIM-HS configs

2019-10-28T19:12:31Z

Starting from nSIM 2019.06 is possible to use DW UART instead of ARC UART. That allows us to merge "nsim_hs" with "haps_hs" and "nsim_hs_smp" with "haps_hs_smp" with minor changes which were done in previous commits. We eliminate nsim_hs_defconfig and nsim_hs_smp_defconfig and leave haps_hs_defconfig and haps_hs_smp_defconfig which can be used on HAPS / nSIM / ZEBU / QEMU platforms without additional changes in Linux kernel. For nSIM we should now use UART property values "-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000" instead of previously used "-prop=nsim_mem-dev=uart0,base=0xc0fc1000" "use_connect" and "irq" values of UART property remains untouched. Signed-off-by: Eugeniy Paltsev Signed-off-by: Vineet Gupta

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

ARC: [plat-sim] Include this platform unconditionally

2017-08-04T08:19:47Z

Essentially remove CONFIG_ARC_PLAT_SIM There is no need for any platform specific code, just the board DTS match strings which we can include unconditionally Signed-off-by: Vineet Gupta

ARC: [plat-*] ARC_HAS_COH_CACHES no longer relevant

2017-02-06T17:37:57Z

A typical SMP system expects cache coherency. Initial NPS platform support was slated to be SMP w/o cache coherency. However it seems the platform now selects that option, so there is no point in keeping it around. Signed-off-by: Vineet Gupta

ARCv2: Add support for ZeBu Emulation platform for HS cores

2016-09-30T21:48:15Z

The cool thing is that same kernel image can run on - nsim OSCI simulation platform - SDPlite FPGA setups Signed-off-by: Vineet Gupta

ARC: remove extraneous header include

2015-11-14T07:41:38Z

Signed-off-by: Vineet Gupta

ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_smp()

2015-10-28T10:43:41Z

MCIP now registers it's own per cpu setup routine (for IPI IRQ request) using smp_ops.init_irq_cpu(). So no need for platforms to do that. This now completely decouples platforms from MCIP. Signed-off-by: Vineet Gupta

ARCv2: smp: [plat-*]: No need to explicitly call mcip_init_early_smp()

2015-10-28T10:43:40Z

MCIP now registers it's own probe callback with smp_ops.init_early_smp() which is called by ARC common code, so no need for platforms to do that. This decouples the platforms and MCIP and helps confine MCIP details to it's own file. Signed-off-by: Vineet Gupta

ARCv2: [nsimhs] Support simulation platforms for HS38x cores

2015-06-25T00:30:19Z

Cc: Grant Likely Cc: Rob Herring Cc: devicetree@vger.kernel.org Signed-off-by: Vineet Gupta

ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al

2015-06-22T08:36:56Z

Cc: Jason Cooper Cc: Thomas Gleixner Signed-off-by: Vineet Gupta