linux-dev/arch/arm/boot/dts/alpine.dtsi, branch linus/master

ARM: dts: alpine: Align GIC nodename with dtschema

2020-09-11T15:44:11Z

Fix dtschema validator warnings like: gic@fb001000: $nodename:0: 'gic@fb001000' does not match '^interrupt-controller(@[0-9a-f,]+)*$' Signed-off-by: Krzysztof Kozlowski

ARM: dts: Kill off skeleton{64}.dtsi

2019-01-30T16:30:31Z

Remove the usage of skeleton.dtsi in the remaining dts files. It was deprecated since commit 9c0da3cc61f1 ("ARM: dts: explicitly mark skeleton.dtsi as deprecated"). This will make adding a unit-address to memory nodes easier. The main tricky part to removing skeleton.dtsi is we could end up with no /memory node at all when a bootloader depends on one being present. I hacked up dtc to check for this condition. Acked-by: Linus Walleij Reviewed-by: Florian Fainelli Reviewed-by: Matthias Brugger Acked-by: Viresh Kumar Acked-by: Alexandre Belloni Acked-by: Neil Armstrong Acked-by: Antoine Tenart Acked-by: Alexandre TORGUE Acked-by: Robert Jarzmik Acked-by: Vladimir Zapolskiy Tested-by: Kevin Hilman Reviewed-by: Kevin Hilman Tested-by: Martin Blumenstingl Reviewed-by: Martin Blumenstingl Signed-off-by: Rob Herring Reviewed-by: Gregory CLEMENT Tested-by: Gregory CLEMENT Signed-off-by: Arnd Bergmann

ARM: dts: alpine: add valid clock-frequency values

2017-04-03T07:06:55Z

Update the Alpine clock-frequency values with valid default values. The bootloader can still update these values if needed, but at least we can boot if it does not. Signed-off-by: Antoine Tenart

ARM: dts: alpine: add spaces before the uart node units.

2017-04-03T07:06:53Z

Cosmetic cleanup to have consistent node definitions. Add a space before the node units which do not have one. Signed-off-by: Antoine Tenart

ARM: dts: alpine: remove 0x's from the uart1 node unit address

2017-04-03T07:06:49Z

Remove 0x's from the uart1 node unit address to have consistent nodes. Signed-off-by: Antoine Tenart

ARM: dts: alpine: fix PCIe node name

2017-03-24T18:22:45Z

PCIe bridges should have a node name of 'pcie'. Signed-off-by: Rob Herring Cc: Tsahee Zidenberg Cc: Antoine Tenart Signed-off-by: Antoine Tenart

ARM: DTS: Fix register map for virt-capable GIC

2017-02-07T14:06:46Z

Since everybody copied my own mistake from the DT binding example, let's address all the offenders in one swift go. Most of them got the CPU interface size wrong (4kB, while it should be 8kB), except for both keystone platforms which got the control interface wrong (4kB instead of 8kB). In a few cases where I knew for sure what implementation was used, I've added the "arm,gic-400" compatible string. I'm 99% sure that this is what everyone is using, but short of having the TRM for all the other SoCs, I've left them alone. Acked-by: Shawn Guo Acked-by: Tony Lindgren Acked-by: Santosh Shilimkar Acked-by: Krzysztof Kozlowski Acked-by: Maxime Ripard Acked-by: Antoine Tenart Acked-by: Arnd Bergmann Acked-by: Matthias Brugger Acked-by: Heiko Stuebner Reviewed-by: Javier Martinez Canillas Signed-off-by: Marc Zyngier Signed-off-by: Arnd Bergmann

ARM: dts: alpine: add the MSIX node

2016-02-26T21:57:46Z

With the newly available MSIX driver for Alpine, add the corresponding node in the Alpine device tree. Signed-off-by: Antoine Tenart Signed-off-by: Arnd Bergmann

ARM: dts: alpine: add internal pci

2015-04-13T23:16:13Z

This patch adds device-tree entry for the internal pci bus on Alpine. Alpine's on-chip devices appear as pci devices on this bus. Signed-off-by: Tsahee Zidenberg Signed-off-by: Arnd Bergmann

ARM: dts: Alpine platform devicetree

2015-03-16T14:34:53Z

This patch introduces devicetree for the Alpine platform, and for a development board based on the same platform. Signed-off-by: Barak Wasserstrom Signed-off-by: Tsahee Zidenberg Acked-by: Arnd Bergmann Signed-off-by: Arnd Bergmann