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<title>linux-dev/arch/arm64/boot/dts/amd, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
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<updated>2022-06-16T20:45:26Z</updated>
<entry>
<title>arm64: dts: amd: adjust whitespace around '='</title>
<updated>2022-06-16T20:45:26Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2022-05-26T20:46:03Z</published>
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<id>urn:sha1:dec1c62e91ba268ab2a6e339d4d7a59287d5eba1</id>
<content type='text'>
Fix whitespace coding style: use single space instead of tabs or
multiple spaces around '=' sign in property assignment.  No functional
changes (same DTB).

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20220526204606.833054-2-krzysztof.kozlowski@linaro.org
</content>
</entry>
<entry>
<title>dt: amd-seattle: add a description of the CPUs and caches</title>
<updated>2022-03-24T18:49:55Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:23:06Z</published>
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<id>urn:sha1:6a2f0b2d3b74e3e4002dc4143887637cd216e531</id>
<content type='text'>
Add a DT description of the CPU and cache hierarchy as found on
the AMD Seattle SOC. Given the tight coupling of the PMU with
the CPUs, move the PMU node into the cpu .dtsi file as well, and
add the missing affinity description.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0</title>
<updated>2022-03-24T18:49:54Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:23:05Z</published>
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<id>urn:sha1:e0db1597a71a7de661a107090554f8b187e77a08</id>
<content type='text'>
Disable some peripherals that are not usable on B0 silicon based
Overdrives.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt: amd-seattle: add description of the SATA/CCP SMMUs</title>
<updated>2022-03-24T18:49:54Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:23:04Z</published>
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<id>urn:sha1:429863e767a084e5de6934d768946cda5793b691</id>
<content type='text'>
Add descriptions of the SMMUs that cover the SATA controller(s)
on the AMD Seattle SOC. The CCP crypto accelerator shares its
SMMU with the second SATA controller, which is only enabled on
B1 silicon.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt: amd-seattle: add a description of the PCIe SMMU</title>
<updated>2022-03-24T18:49:54Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:23:03Z</published>
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<id>urn:sha1:dd5c160655e24c1a86b1f23e870b69f6aaa80646</id>
<content type='text'>
Add a description of the SMMU that covers the PCIe host bridge
on AMD Seattle.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt: amd-seattle: fix PCIe legacy interrupt routing</title>
<updated>2022-03-24T18:49:54Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:23:02Z</published>
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<id>urn:sha1:acd9208ef8a4e1dc0e1d835fab284ca717a01f93</id>
<content type='text'>
The AMD Seattle SOC can be configured to expose up to 3 PCIe root
ports, each of which is wired to 4 dedicated SPI wired interrupts
for legacy INTx support. Update the SOC DT description to reflect
this.

Fix a stale comment about the size of the MMIO64 resource window
while at it.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding</title>
<updated>2022-03-24T18:49:54Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:23:01Z</published>
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<id>urn:sha1:9bd9a063accf15b8ddae15e17d9d6312a31e4464</id>
<content type='text'>
Upgrade the DT descriptions of the AMD Seattle XGBE network
controllers to use the current SMMU bindings.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt: amd-seattle: remove Overdrive revision A0 support</title>
<updated>2022-03-24T18:49:53Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:23:00Z</published>
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<id>urn:sha1:f179eb6b3cc35b451820468a3d09fe169416d4bc</id>
<content type='text'>
Support for AMD Seattle silicon revision A0 is no longer relevant,
since we no longer have a driver for the network controller, and
the PCIe on these boards was very unreliable. So drop the DTS
description of the A0 version of the overdrive board.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt: amd-seattle: remove Husky platform</title>
<updated>2022-03-24T18:49:53Z</updated>
<author>
<name>Ard Biesheuvel</name>
<email>ardb@kernel.org</email>
</author>
<published>2019-12-03T15:22:59Z</published>
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<id>urn:sha1:a4eb44a6435d6d8f9e642407a4a06f65eb90ca04</id>
<content type='text'>
The Huskyboard never made it to production, and its successor the
Celloboard was only shipped in very limited quantities with ACPI
only firmware, so the historical significance of husky.dts is
highly questionable. Let's drop it.

Signed-off-by: Ard Biesheuvel &lt;ardb@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>arm64: dts: amd: Fix SPI bus warnings</title>
<updated>2018-09-28T10:32:51Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2018-09-13T18:12:40Z</published>
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<id>urn:sha1:e9f0878c4b2004ac19581274c1ae4c61ae3ca70e</id>
<content type='text'>
dtc has new checks for SPI buses. Fix the warnings in node names.

arch/arm64/boot/dts/amd/amd-overdrive.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dtb: Warning (spi_bus_bridge): /smb/ssp@e1030000: node name for SPI buses should be 'spi'

Cc: Brijesh Singh &lt;brijeshkumar.singh@amd.com&gt;
Cc: Suravee Suthikulpanit &lt;suravee.suthikulpanit@amd.com&gt;
Cc: Tom Lendacky &lt;thomas.lendacky@amd.com&gt;
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
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