<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/arm64/boot/dts/marvell/Makefile, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/arm64/boot/dts/marvell/Makefile?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/arm64/boot/dts/marvell/Makefile?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-09-02T16:11:27Z</updated>
<entry>
<title>arm64: dts: marvell: add support for Methode eDPU</title>
<updated>2022-09-02T16:11:27Z</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2022-05-16T12:48:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=1a9f9785a9abe3f55e874a47cb0c483c99b55e83'/>
<id>urn:sha1:1a9f9785a9abe3f55e874a47cb0c483c99b55e83</id>
<content type='text'>
Methode eDPU is an Armada 3720 powered board based on the Methode uDPU.

They feature the same CPU, RAM, and storage as well as the form factor.

However, eDPU only has one SFP slot plus a copper G.hn port.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board</title>
<updated>2022-07-19T13:12:43Z</updated>
<author>
<name>Chris Packham</name>
<email>chris.packham@alliedtelesis.co.nz</email>
</author>
<published>2022-07-05T19:09:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b795fadfc46bc497257435d4d9e57f487f521fd1'/>
<id>urn:sha1:b795fadfc46bc497257435d4d9e57f487f521fd1</id>
<content type='text'>
The 98DX2530 SoC is the Control and Management CPU integrated into
the Marvell 98DX25xx and 98DX35xx series of switch chip (internally
referred to as AlleyCat5 and AlleyCat5X).

These files have been taken from the Marvell SDK and lightly cleaned
up with the License and copyright retained.

gregory.clement: use specific cpu type: cortex-a55 instead of armv8 in
cpu nodes, armv8 being reserved for the arm virtual models that are
not meant to implement a particular CPU type.

Signed-off-by: Chris Packham &lt;chris.packham@alliedtelesis.co.nz&gt;
Signed-off-by: Vadym Kochan &lt;vadym.kochan@plvision.eu&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: marvell: add Globalscale MOCHAbin</title>
<updated>2021-10-13T14:45:59Z</updated>
<author>
<name>Robert Marko</name>
<email>robert.marko@sartura.hr</email>
</author>
<published>2021-10-08T20:53:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=73792919128304938412194d047be3c61cccc76d'/>
<id>urn:sha1:73792919128304938412194d047be3c61cccc76d</id>
<content type='text'>
Globalscale MOCHAbin is a Armada 7040 based development board.

Specifications:
* Armada 7040 Quad core ARMv8 Cortex A-72 @ 1.4GHz
* 2 / 4 / 8 GB of DDR4 DRAM
* 16 GB eMMC
* 4MB SPI-NOR (Bootloader)
* 1x M.2-2280 B-key socket (for SSD expansion, SATA3 only)
* 1x M.2-2250 B-key socket (for modems, USB2.0 and I2C only)
* 1x Mini-PCIe 3.0 (x1, USB2.0 and I2C)
* 1x SATA 7+15 socket (SATA3)
* 1x 16-pin (2×8) MikroBus Connector
* 1x SIM card slot (Connected to the mini-PCIe and both M.2 slots)
* 2x USB3.0 Type-A ports via SMSC USB5434B hub
* Cortex 2x5 JTAG
* microUSB port for UART (PL2303GL/PL2303SA onboard)
* 1x 10G SFP+
* 1x 1G SFP (Connected to 88E1512 PHY)
* 1x 1G RJ45 with PoE PD (Connected to 88E1512 PHY)
* 4x 1G RJ45 ports via Topaz 88E6141 switch
* RTC with battery holder (SoC provided, requires CR2032 battery)
* 1x 12V DC IN
* 1x Power switch
* 1x 12V fan header (3-pin, power only)
* 1x mini-PCIe LED header (2x0.1" pins)
* 1x M.2-2280 LED header (2x0.1" pins)
* 6x Bootstrap jumpers
* 1x Power LED (Green)
* 3x Tri-color RGB LEDs (Controllable)
* 1x Microchip ATECC608B secure element

Note that 1G SFP and 1G WAN cannot be used at the same time as they are in
parallel connected to the same PHY.

Signed-off-by: Robert Marko &lt;robert.marko@sartura.hr&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: add support for Marvell cn9130-crb platform</title>
<updated>2021-07-23T12:34:26Z</updated>
<author>
<name>Konstantin Porotchkin</name>
<email>kostap@marvell.com</email>
</author>
<published>2021-07-08T12:46:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5c0ee54723f3efd80933311080989611302c751f'/>
<id>urn:sha1:5c0ee54723f3efd80933311080989611302c751f</id>
<content type='text'>
The Marvell reference platform CN9130-CRB is a small form factor
board in a metal case. The platform is based on CN9130 SoC with
addition of 8 Gigabit ports SOHO Ethernet switch.
The reference platform features the following:
* Up to 4 CPU cores ARMv8 Cortex-A72 CPU
* CPU core operating speed of up to 2.2GHz
* DDR4 DIMM – 8GB 64bit+ECC @ 2400Mhz.
* 1x eMMC 8GB device
* 1x uSD card 4 bits port on CP
* 1x 128MB SPI NOR flash memory
* 1x USB 3.0 Host port (Type A)
* 1x SATA Gen3 via M.2
* 1x USB 3.0 via M.2
* 1x SIM card slot
* 1x 1G Ethernet port via RGMII
* 1x 10G switch port over SFP+ connector
* 8x 1G ports through 88E6393X switch via XFI
* 1x 2.5G/1G/100M/10M port via HS_SGMII
* 1x PCI Express (PCIe)x1 Gen 3.0
* 1x PCI Express (PCIe)x4 Gen 3.0 via NVMe M.2
* JTAG port

The CRB board uses MCP23017 i2c pin controller that drives the
onboard eMMC abd USB 3,0 port power lines.
The following configuration should be enabled for this controller
support:
CONFIG_PINCTRL_MCP23S08=y

The plaform supports two HW configurations - "A" and "B"
CN9130-CRB-A
* AP-MPP configuration: SDIO, UART
* CP0 Serdes configuration:
	* Lane0-3: NVMe (PCIe x4)
	* Lane4: XFI
	* Lane5: HS_SGMII

2. CN9130-CRB-B
* AP-MPP configuration: SDIO, UART
* CP0-MPP configuration: RGMII, SDIO, I2C0, I2C1, SMI, XSMI
* CP0 Serdes configuration:
	* Lane0: PCIe x1
	* Lane1: USB3_0 x1
	* Lane2: SATA x1
	* Lane3: USB3_1 x1
	* Lane4: XFI
	* Lane5: HS_SGMII

Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: cn913x: add device trees for topology B boards</title>
<updated>2021-07-23T12:33:11Z</updated>
<author>
<name>Konstantin Porotchkin</name>
<email>kostap@marvell.com</email>
</author>
<published>2021-07-08T12:46:09Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4c43a41e5b8ccbeee79330ae7989c301589d38c2'/>
<id>urn:sha1:4c43a41e5b8ccbeee79330ae7989c301589d38c2</id>
<content type='text'>
The CN913x DB with topology B is similar to a regular setup (A)
boards, but uses NAND flash as a boot device, while topology A
boards are booting from SPI flash.
Since NAND and SPI on CN913x DB boards share some wires, they
cannot be activated simultaneously.
The DTS files for setup "B" are based on setup "A", in which the
CP0 NAND controller enabled and CP0 SPI1 disabled.

Signed-off-by: Konstantin Porotchkin &lt;kostap@marvell.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: marvell: add DT for ESPRESSObin-Ultra</title>
<updated>2020-11-29T11:15:06Z</updated>
<author>
<name>Vladimir Vid</name>
<email>vladimir.vid@sartura.hr</email>
</author>
<published>2020-10-26T18:44:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3404fe15a60fe790799d6e1dd5de51997f338cc6'/>
<id>urn:sha1:3404fe15a60fe790799d6e1dd5de51997f338cc6</id>
<content type='text'>
This adds support for ESPRESSObin-Ultra from Globalscale.

Specifications are similar to the base ESPRESSObin board, with main
difference being being WAN port with PoE capability and 2 additional ethernet ports.

Full specifications:

1x Marvell 64 bit Dual Core ARM A53 Armada 3700 SOC clocked up to 1.2Ghz
1x Topaz 6341 Networking Switch
1GB DDR4
8GB eMMC
1x WAN with 30W POE
4x Gb LAN
1x RTC Clock and battery
1x DC Jack
1x USB 3.0 Type A
1x USB 2.0 Type A
1x SIM NanoSIM card Slot
1x Power Button
4x LED
1x Reset button
1x microUSB for UART
1x M.2 2280 slot for memory
1x 2x2 802.11ac Wi-Fi
1x MiniPCIE slot for Wi-Fi (PCIe interface)

Signed-off-by: Vladimir Vid &lt;vladimir.vid@sartura.hr&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: marvell: Add a device tree for the IEI Puzzle-M801 board</title>
<updated>2020-11-29T11:05:09Z</updated>
<author>
<name>Luka Kovacic</name>
<email>luka.kovacic@sartura.hr</email>
</author>
<published>2020-10-25T01:13:51Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=6d96e11b777129d709096744e125bd866ff8b5a1'/>
<id>urn:sha1:6d96e11b777129d709096744e125bd866ff8b5a1</id>
<content type='text'>
Add initial support for the IEI Puzzle-M801 1U Rackmount Network
Appliance board.

The board is based on the quad-core Marvell Armada 8040 SoC and supports
up to 16 GB of DDR4 2400 MHz ECC RAM. It has a PCIe x16 slot (x2 lanes
only) and an M.2 type B slot.

Main system hardware:
2x USB 3.0
4x Gigabit Ethernet
2x SFP+
1x SATA 3.0
1x M.2 type B
1x RJ45 UART
1x SPI flash
1x IEI WT61P803 PUZZLE Microcontroller
1x EPSON RX8010 RTC (used instead of the integrated Marvell RTC controller)
6x SFP+ LED
1x HDD LED

All of the hardware listed above is supported and tested in this port.

Signed-off-by: Luka Kovacic &lt;luka.kovacic@sartura.hr&gt;
Acked-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Cc: Luka Perkov &lt;luka.perkov@sartura.hr&gt;
Cc: Robert Marko &lt;robert.marko@sartura.hr&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: marvell: build ESPRESSObin variants</title>
<updated>2020-03-15T09:36:43Z</updated>
<author>
<name>Tomasz Maciej Nowak</name>
<email>tmn505@gmail.com</email>
</author>
<published>2020-02-27T16:48:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=004c64a8ea040813f968e5782fa04d2ab04a93e9'/>
<id>urn:sha1:004c64a8ea040813f968e5782fa04d2ab04a93e9</id>
<content type='text'>
The commit adding ESPRESSObin variants didn't include those in Makefile to
be built.

Fixes: 447b8789359f ("arm64: dts: marvell: add ESPRESSObin variants")
Signed-off-by: Tomasz Maciej Nowak &lt;tmn505@gmail.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: marvell: Add support for Marvell CN9132-DB</title>
<updated>2019-10-09T07:36:41Z</updated>
<author>
<name>Grzegorz Jaszczyk</name>
<email>jaz@semihalf.com</email>
</author>
<published>2019-10-04T14:27:38Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e1bd6ca9f8be4ec14149d01baf27583bbb5c740b'/>
<id>urn:sha1:e1bd6ca9f8be4ec14149d01baf27583bbb5c740b</id>
<content type='text'>
Extend the support of the CN9131 with yet another additional CP115.

The last number indicates how many external CP115 are used.

New available interfaces:
* CP2 CRYPTO-0 (disabled)
* CP2 ETH-0 (SFI, problem with the SFP cage, disabled)
* CP2 GPIO-1
* CP2 GPIO-2
* CP2 I2C-0
* CP2 PCIe-0 x2
* CP2 PCIe-2 x1 (disabled)
* CP2 SDHCI-0
* CP2 USB3-1 (High-speed)

Signed-off-by: Grzegorz Jaszczyk &lt;jaz@semihalf.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
<entry>
<title>arm64: dts: marvell: Add support for Marvell CN9131-DB</title>
<updated>2019-10-09T07:36:41Z</updated>
<author>
<name>Grzegorz Jaszczyk</name>
<email>jaz@semihalf.com</email>
</author>
<published>2019-10-04T14:27:37Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=fe5e610f16a3e210e4f9e56b370dcbb8cb547e76'/>
<id>urn:sha1:fe5e610f16a3e210e4f9e56b370dcbb8cb547e76</id>
<content type='text'>
Extend the support of the CN9130 by adding an external CP115.

The last number indicates how many external CP115 are used.

New available interfaces:
* CP1 CRYPTO-0 (disabled)
* CP1 ETH-0 (SFI, problem with the SFP cage, disabled)
* CP1 GPIO-1
* CP1 GPIO-2
* CP1 I2C-0
* CP1 PCIe-0 x2
* CP1 SPI-1
* CP1 SATA-0-1
* CP1 USB3-1

Signed-off-by: Grzegorz Jaszczyk &lt;jaz@semihalf.com&gt;
Signed-off-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
</content>
</entry>
</feed>
