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<title>linux-dev/arch/arm64/boot/dts/nvidia, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/arm64/boot/dts/nvidia?h=linus%2Fmaster</id>
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<updated>2022-05-04T09:22:43Z</updated>
<entry>
<title>arm64: tegra: Add missing DFLL reset on Tegra210</title>
<updated>2022-05-04T09:22:43Z</updated>
<author>
<name>Diogo Ivo</name>
<email>diogo.ivo@tecnico.ulisboa.pt</email>
</author>
<published>2022-04-29T12:58:43Z</published>
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<id>urn:sha1:0017f2c856e21bb900be88469e15dac4f41f4065</id>
<content type='text'>
Commit 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling
clocks") removed deassertion of reset lines when enabling peripheral
clocks. This breaks the initialization of the DFLL driver which relied
on this behaviour.

In order to be able to fix this, add the corresponding reset to the DT.
Tested on Google Pixel C.

Cc: stable@vger.kernel.org
Fixes: 4782c0a5dd88 ("clk: tegra: Don't deassert reset on enabling clocks")
Signed-off-by: Diogo Ivo &lt;diogo.ivo@tecnico.ulisboa.pt&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Add memory controller channels</title>
<updated>2022-04-29T08:36:01Z</updated>
<author>
<name>Ashish Mhetre</name>
<email>amhetre@nvidia.com</email>
</author>
<published>2022-04-26T07:38:27Z</published>
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<id>urn:sha1:000b99e5ed1c9e33c14f3582474ae55cd739ae8d</id>
<content type='text'>
From tegra186 onwards, memory controller support multiple channels.
During the error interrupts from memory controller, corresponding
channels need to be accessed for logging error info and clearing the
interrupt.
So add address and size of these channels in device tree node of
tegra186, tegra194 and tegra234 memory controller. Also add reg-names
for each of these reg items which are used by driver for mapping.

Signed-off-by: Ashish Mhetre &lt;amhetre@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Enable ASRC on various platforms</title>
<updated>2022-04-26T13:13:19Z</updated>
<author>
<name>Sameer Pujar</name>
<email>spujar@nvidia.com</email>
</author>
<published>2022-03-31T14:03:32Z</published>
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<id>urn:sha1:261a46a977c6babde207d5e979fe5cf779b067b9</id>
<content type='text'>
Enable ASRC module usage on various Jetson Platforms. This can be plugged
into an audio path using ALSA mixer controls.

Signed-off-by: Sameer Pujar &lt;spujar@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Add ASRC device on Tegra186 and later</title>
<updated>2022-04-26T13:12:54Z</updated>
<author>
<name>Sameer Pujar</name>
<email>spujar@nvidia.com</email>
</author>
<published>2022-03-31T14:03:31Z</published>
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<id>urn:sha1:47a08153f32dc7d38953c84e3f2c07059411ce66</id>
<content type='text'>
Asynchronous Sample Rate Converter (ASRC) is a client of AHUB and is
present on Tegra186 and later generations of Tegra SoC. Add this device
on the relevant SoC DTSI files.

Signed-off-by: Sameer Pujar &lt;spujar@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Update PWM fan node name</title>
<updated>2022-04-25T19:15:33Z</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2022-04-06T15:26:55Z</published>
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<id>urn:sha1:6d9d19af3e34121a816757b4fae341a4d749e1a7</id>
<content type='text'>
According to the device-tree binding document for PWM fans [0], the
PWM fan node name should be 'pwm-fan'. Update the PWM fan node name to
align with this.

[0] Documentation/devicetree/bindings/hwmon/pwm-fan.txt

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Add node for Tegra234 CCPLEX cluster</title>
<updated>2022-04-25T16:12:00Z</updated>
<author>
<name>Sumit Gupta</name>
<email>sumitg@nvidia.com</email>
</author>
<published>2022-04-05T13:01:19Z</published>
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<id>urn:sha1:962c400d48e604438cfb3732016ad1b74bfc298c</id>
<content type='text'>
Adding CCPLEX cluster node to represent Tegra234 cpufreq. Tegra234 uses
some of the CRAB (Control Register Access Bus) registers for CPU
frequency requests. These registers are memory mapped to the
CCPLEX_MMCRAB_ARM region. In this node, mapping the range of MMCRAB
registers is required only for CPU frequency info.

Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Add QSPI controllers on Tegra234</title>
<updated>2022-04-06T13:27:17Z</updated>
<author>
<name>Ashish Singhal</name>
<email>ashishsingha@nvidia.com</email>
</author>
<published>2022-03-08T18:30:26Z</published>
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<id>urn:sha1:71f69ffa0129bf04205edf0e7dc73dc4777b2588</id>
<content type='text'>
This adds the QSPI controllers on the Tegra234 SoC and populates the
SPI NOR flash device for the Jetson AGX Orin platform.

Signed-off-by: Ashish Singhal &lt;ashishsingha@nvidia.com&gt;
Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Signed-off-by: Krishna Yarlagadda &lt;kyarlagadda@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>arm64: tegra: Update SDMMC1/3 clock source for Tegra194</title>
<updated>2022-04-06T13:22:39Z</updated>
<author>
<name>Aniruddha Rao</name>
<email>anrao@nvidia.com</email>
</author>
<published>2022-03-16T09:44:45Z</published>
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<id>urn:sha1:7ac853ba789d1d9fb22b05f4ebd3a37fd1bb11c1</id>
<content type='text'>
The default parent for SDMMC1/3 clock sources can provide maximum frequency
of 136MHz for SDR104 mode.
Update parent clock source for SDMMC1/SDMMC3 instances
to increase the output clock frequency to 195MHz and improve the perf.

Signed-off-by: Aniruddha Rao &lt;anrao@nvidia.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2022-03-24T01:37:22Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-03-24T01:37:22Z</published>
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<id>urn:sha1:ed4643521e6af8ab8ed1e467630a85884d2696cf</id>
<content type='text'>
Pull ARM devicetree updates from Arnd Bergmann:
 "After a somewhat quiet 5.17 release, the size of the DT changes is a
  bit larger again. There are nine new SoC that get added, all of them
  related to existing platforms:

   - Airoha (formerly Mediatek/EcoNet) EN7523 networking SoC and EVB

   - Mediatek mt6582 tablet platform with the Prestigio PMT5008 3G
     tablet

   - Microchip Lan966 networking SoC and it evaluation board

   - Qualcomm Snapdragon 625/632 midrange phone SoCs, with the LG Nexus
     5X and Fairphone FP3 phones

   - Renesas RZ/G2LC and RZ/V2L general-purpose embedded SoCs, along
     with their evaluation boards

   - Samsung Exynos 850 phone SoC and reference board

   - Samsung Exynos7885 with the Samsung Galaxy A8 (2018) phone

   - Tesla FSD (Fully Self-Driving), an automotive SoC loosely derived
     from the Samsung Exynos family.

   - TI K3/AM62 SoC and reference board

  Support for additional functionality in existing dts files is added
  all over the place: Samsung, Renesas, Mstar, wpcm450, OMAP, AT91,
  Allwinner, i.MX, Tegra, Aspeed, Oxnas, Qualcomm, Mediatek, and
  Broadcom.

  Samsung has a rework for its pinctrl schema that is a bit tricky and
  requires driver changes to be included here.

  A few more platforms only have smaller cleanups and DT Schema fixes,
  this includes SoCFPGA, ux500, ixp4xx, STi, Xilinx Zynq, LG, and Juno.

  The new machines are really too many to list, but I'll do it anyway:

  Allwinner:
   - A20-Marsboard development board

  Amlogic:
   - Amediatek X96-AIR (Amlogic S905X3)
   - CYX A95XF3-AIR (Amlogic S905X3)
   - Haochuangy H96-Max (Amlogic S905X3)
   - Amlogic AQ222 (Amlogic S4)
   - OSMC Vero 4K+ (Amlogic S905D)

  Arm Juno:
   - Separate DT depending on SCMI firmware version

  Aspeed:
   - Quanta S6Q BMC (AST2600)
   - ASRock ROMED8HM3 (AST2500)

  Broadcom:
   - Raspberry Pi Zero 2 W

  Marvell MVEBU/Armada:
   - Ctera C200 V1 NAS (kirkwood)
   - Ctera C200 V2 NAS (armada-370)

  Mstar:
   - DongShanPiOne, a low-end embedded board
   - Miyoo Mini handheld game console

  NXP i.MX:
   - Numerous i.MX8M Mini based boards in even more variations, but
    none based on other SoCs this time:
    Protonic PRT8MM, emCON-MX8M Mini, Toradex Verdin, and
    Gateworks GW7903

  Qualcomm:
   - Google Herobrine R1 Chromebook platform (Snapdragon 7c Gen 3)
   - SHIFT6mq phone (Snapdragon 845)
   - Samsung Galaxy Book2 (Snapdragon 850)
   - Snapdragon 8 Gen 1 Hardware Development Kit

  TI OMAP:
   - SanCloud BeagleBone Enhanced WiFi

  Rockchip:
   - Pine64 PineNote ereader tablet (rk356x)
   - Bananapi-R2-Pro (rk356x)

  STM32:
   - emtrion emSBS-Argon embedded board (stm32mp157c)"

* tag 'arm-dt-5.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (627 commits)
  arm64: dts: n5x: drop invalid property and fix edac node name
  arm64: dts: fsd: Add the MCT support
  arm64: dts: stingray: Fix spi clock name
  arm64: dts: ns2: Fix spi clock name
  ARM: dts: rockchip: Update regulator name for PX3
  ARM: dts: rockchip: Add #clock-cells value for rk805
  arm64: dts: rockchip: Add #clock-cells value for rk805
  arm64: dts: rockchip: Remove vcc13 and vcc14 for rk808
  arm64: dts: rockchip: Fix SDIO regulator supply properties on rk3399-firefly
  ARM: dts: at91: sama7g5: Add NAND support
  ARM: dts: at91: sama7g5: add eic node
  ARM: dts: at91: sama7g5: Remove unused properties in i2c nodes
  ARM: dts: at91: sam9x60ek: modify vdd_1v5 regulator to vdd_1v15
  arm64: dts: lg: align pl330 node name with dtschema
  arm64: dts: lg: add dma-cells to pl330 node
  arm64: dts: juno: align pl330 node name with dtschema
  arm64: dts: broadcom: Fix sata nodename
  arm64: dts: n5x: add sdr edac support
  arm64: dts: agilex/stratix10: add clock-names to USB DWC2 node
  dt-bindings: usb: dwc2: add disable-over-current
  ...
</content>
</entry>
<entry>
<title>Merge tag 'tegra-for-5.17-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes</title>
<updated>2022-03-07T22:23:58Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2022-03-07T22:23:56Z</published>
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<id>urn:sha1:537c3757b4e3116ad5ab039029b830224f9154d9</id>
<content type='text'>
arm64: tegra: Device tree fixes for v5.17

This contains a single, last-minute fix to disable the display SMMU by
default because under some circumstances leaving it enabled by default
can cause SMMU faults on boot.

* tag 'tegra-for-5.17-arm64-dt-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  arm64: tegra: Disable ISO SMMU for Tegra194

Link: https://lore.kernel.org/r/20220307182120.2169598-1-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
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