<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/arm64/include/asm/pgtable-2level-hwdef.h, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/arm64/include/asm/pgtable-2level-hwdef.h?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/arm64/include/asm/pgtable-2level-hwdef.h?h=master'/>
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<updated>2014-07-23T14:27:51Z</updated>
<entry>
<title>arm64: Remove asm/pgtable-*level-hwdef.h files</title>
<updated>2014-07-23T14:27:51Z</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2014-07-15T15:35:38Z</published>
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<id>urn:sha1:6b4fee241dd7c4b11cae4432bfa899a386d71f26</id>
<content type='text'>
The macros in these files can easily be computed based on PAGE_SHIFT and
VA_BITS, so just remove them and add the corresponding macros to
asm/pgtable-hwdef.h

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Tested-by: Jungseok Lee &lt;jungseoklee85@gmail.com&gt;
</content>
</entry>
<entry>
<title>arm64: Use 42-bit address space with 64K pages</title>
<updated>2013-11-05T17:23:52Z</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2013-10-23T15:50:07Z</published>
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<id>urn:sha1:847264fb7e73ade5b5e4b6eea3daa243a1f5217e</id>
<content type='text'>
This patch expands the VA_BITS to 42 when the 64K page configuration is
enabled allowing 2TB kernel linear mapping. Linux still uses 2 levels of
page tables in this configuration with pgd now being a full page.

Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Will Deacon &lt;will.deacon@arm.com&gt;
Acked-by: Marc Zyngier &lt;marc.zyngier@arm.com&gt;
</content>
</entry>
<entry>
<title>arm64: MMU definitions</title>
<updated>2012-09-17T12:41:56Z</updated>
<author>
<name>Catalin Marinas</name>
<email>catalin.marinas@arm.com</email>
</author>
<published>2012-03-05T11:49:27Z</published>
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<id>urn:sha1:4f04d8f00545110a0e525ae2fb62ab38cb417236</id>
<content type='text'>
The virtual memory layout is described in
Documentation/arm64/memory.txt. This patch adds the MMU definitions for
the 4KB and 64KB translation table configurations. The SECTION_SIZE is
2MB with 4KB page and 512MB with 64KB page configuration.

PHYS_OFFSET is calculated at run-time and stored in a variable (no
run-time code patching at this stage).

On the current implementation, both user and kernel address spaces are
512G (39-bit) each with a maximum of 256G for the RAM linear mapping.
Linux uses 3 levels of translation tables with the 4K page configuration
and 2 levels with the 64K configuration. Extending the memory space
beyond 39-bit with the 4K pages or 42-bit with 64K pages requires an
additional level of translation tables.

The SPARSEMEM configuration is global to all AArch64 platforms and
allows for 1GB sections with SPARSEMEM_VMEMMAP enabled by default.

Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Tony Lindgren &lt;tony@atomide.com&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Acked-by: Olof Johansson &lt;olof@lixom.net&gt;
Acked-by: Santosh Shilimkar &lt;santosh.shilimkar@ti.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
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