<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/arm64/kvm/vgic, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/arm64/kvm/vgic?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/arm64/kvm/vgic?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-06-08T09:16:15Z</updated>
<entry>
<title>KVM: arm64: Replace vgic_v3_uaccess_read_pending with vgic_uaccess_read_pending</title>
<updated>2022-06-08T09:16:15Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-06-07T13:14:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=98432ccdec9f178ba041e1e5f9f32dbd71576504'/>
<id>urn:sha1:98432ccdec9f178ba041e1e5f9f32dbd71576504</id>
<content type='text'>
Now that GICv2 has a proper userspace accessor for the pending state,
switch GICv3 over to it, dropping the local version, moving over the
specific behaviours that CGIv3 requires (such as the distinction
between pending latch and line level which were never enforced
with GICv2).

We also gain extra locking that isn't really necessary for userspace,
but that's a small price to pay for getting rid of superfluous code.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Reviewed-by: Eric Auger &lt;eric.auger@redhat.com&gt;
Link: https://lore.kernel.org/r/20220607131427.1164881-3-maz@kernel.org
</content>
</entry>
<entry>
<title>KVM: arm64: Don't read a HW interrupt pending state in user context</title>
<updated>2022-06-07T15:28:19Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-06-07T13:14:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2cdea19a34c2340b3aa69508804efe4e3750fcec'/>
<id>urn:sha1:2cdea19a34c2340b3aa69508804efe4e3750fcec</id>
<content type='text'>
Since 5bfa685e62e9 ("KVM: arm64: vgic: Read HW interrupt pending state
from the HW"), we're able to source the pending bit for an interrupt
that is stored either on the physical distributor or on a device.

However, this state is only available when the vcpu is loaded,
and is not intended to be accessed from userspace. Unfortunately,
the GICv2 emulation doesn't provide specific userspace accessors,
and we fallback with the ones that are intended for the guest,
with fatal consequences.

Add a new vgic_uaccess_read_pending() accessor for userspace
to use, build on top of the existing vgic_mmio_read_pending().

Reported-by: Eric Auger &lt;eric.auger@redhat.com&gt;
Reviewed-by: Eric Auger &lt;eric.auger@redhat.com&gt;
Tested-by: Eric Auger &lt;eric.auger@redhat.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Fixes: 5bfa685e62e9 ("KVM: arm64: vgic: Read HW interrupt pending state from the HW")
Link: https://lore.kernel.org/r/20220607131427.1164881-2-maz@kernel.org
Cc: stable@vger.kernel.org
</content>
</entry>
<entry>
<title>Merge tag 'kvmarm-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into HEAD</title>
<updated>2022-05-25T09:09:23Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2022-05-20T11:16:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=47e8eec83262083c7da220446551eaad614218ea'/>
<id>urn:sha1:47e8eec83262083c7da220446551eaad614218ea</id>
<content type='text'>
KVM/arm64 updates for 5.19

- Add support for the ARMv8.6 WFxT extension

- Guard pages for the EL2 stacks

- Trap and emulate AArch32 ID registers to hide unsupported features

- Ability to select and save/restore the set of hypercalls exposed
  to the guest

- Support for PSCI-initiated suspend in collaboration with userspace

- GICv3 register-based LPI invalidation support

- Move host PMU event merging into the vcpu data structure

- GICv3 ITS save/restore fixes

- The usual set of small-scale cleanups and fixes

[Due to the conflict, KVM_SYSTEM_EVENT_SEV_TERM is relocated
 from 4 to 6. - Paolo]
</content>
</entry>
<entry>
<title>Merge branch kvm-arm64/its-save-restore-fixes-5.19 into kvmarm-master/next</title>
<updated>2022-05-16T16:48:36Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-05-16T16:48:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5c0ad551e9aa6188f2bda0977c1cb6768a2b74ef'/>
<id>urn:sha1:5c0ad551e9aa6188f2bda0977c1cb6768a2b74ef</id>
<content type='text'>
* kvm-arm64/its-save-restore-fixes-5.19:
  : .
  : Tighten the ITS save/restore infrastructure to fail early rather
  : than late. Patches courtesy of Rocardo Koller.
  : .
  KVM: arm64: vgic: Undo work in failed ITS restores
  KVM: arm64: vgic: Do not ignore vgic_its_restore_cte failures
  KVM: arm64: vgic: Add more checks when restoring ITS tables
  KVM: arm64: vgic: Check that new ITEs could be saved in guest memory

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>Merge branch kvm-arm64/misc-5.19 into kvmarm-master/next</title>
<updated>2022-05-16T16:48:36Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-05-16T16:48:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=822ca7f82b21822bb7435a6d76feffe60a86ec40'/>
<id>urn:sha1:822ca7f82b21822bb7435a6d76feffe60a86ec40</id>
<content type='text'>
* kvm-arm64/misc-5.19:
  : .
  : Misc fixes and general improvements for KVMM/arm64:
  :
  : - Better handle out of sequence sysregs in the global tables
  :
  : - Remove a couple of unnecessary loads from constant pool
  :
  : - Drop unnecessary pKVM checks
  :
  : - Add all known M1 implementations to the SEIS workaround
  :
  : - Cleanup kerneldoc warnings
  : .
  KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
  KVM: arm64: pkvm: Don't mask already zeroed FEAT_SVE
  KVM: arm64: pkvm: Drop unnecessary FP/SIMD trap handler
  KVM: arm64: nvhe: Eliminate kernel-doc warnings
  KVM: arm64: Avoid unnecessary absolute addressing via literals
  KVM: arm64: Print emulated register table name when it is unsorted
  KVM: arm64: Don't BUG_ON() if emulated register table is unsorted

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>KVM: arm64: vgic: Undo work in failed ITS restores</title>
<updated>2022-05-16T12:58:04Z</updated>
<author>
<name>Ricardo Koller</name>
<email>ricarkol@google.com</email>
</author>
<published>2022-05-10T00:16:33Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8c5e74c90bb522181dfb051fffff3dad702e704d'/>
<id>urn:sha1:8c5e74c90bb522181dfb051fffff3dad702e704d</id>
<content type='text'>
Failed ITS restores should clean up all state restored until the
failure. There is some cleanup already present when failing to restore
some tables, but it's not complete. Add the missing cleanup.

Note that this changes the behavior in case of a failed restore of the
device tables.

	restore ioctl:
	1. restore collection tables
	2. restore device tables

With this commit, failures in 2. clean up everything created so far,
including state created by 1.

Reviewed-by: Eric Auger &lt;eric.auger@redhat.com&gt;
Signed-off-by: Ricardo Koller &lt;ricarkol@google.com&gt;
Reviewed-by: Oliver Upton &lt;oupton@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20220510001633.552496-5-ricarkol@google.com
</content>
</entry>
<entry>
<title>KVM: arm64: vgic: Do not ignore vgic_its_restore_cte failures</title>
<updated>2022-05-16T12:58:04Z</updated>
<author>
<name>Ricardo Koller</name>
<email>ricarkol@google.com</email>
</author>
<published>2022-05-10T00:16:32Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=a1ccfd6f6e06eceb632cc29c4f15a32860f05a7e'/>
<id>urn:sha1:a1ccfd6f6e06eceb632cc29c4f15a32860f05a7e</id>
<content type='text'>
Restoring a corrupted collection entry (like an out of range ID) is
being ignored and treated as success. More specifically, a
vgic_its_restore_cte failure is treated as success by
vgic_its_restore_collection_table.  vgic_its_restore_cte uses positive
and negative numbers to return error, and +1 to return success.  The
caller then uses "ret &gt; 0" to check for success.

Fix this by having vgic_its_restore_cte only return negative numbers on
error.  Do this by changing alloc_collection return codes to only return
negative numbers on error.

Signed-off-by: Ricardo Koller &lt;ricarkol@google.com&gt;
Reviewed-by: Oliver Upton &lt;oupton@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20220510001633.552496-4-ricarkol@google.com
</content>
</entry>
<entry>
<title>KVM: arm64: vgic: Add more checks when restoring ITS tables</title>
<updated>2022-05-16T12:58:04Z</updated>
<author>
<name>Ricardo Koller</name>
<email>ricarkol@google.com</email>
</author>
<published>2022-05-10T00:16:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=243b1f6c8f0748bd7b03eab17323f1187e580771'/>
<id>urn:sha1:243b1f6c8f0748bd7b03eab17323f1187e580771</id>
<content type='text'>
Try to improve the predictability of ITS save/restores (and debuggability
of failed ITS saves) by failing early on restore when trying to read
corrupted tables.

Restoring the ITS tables does some checks for corrupted tables, but not as
many as in a save: an overflowing device ID will be detected on save but
not on restore.  The consequence is that restoring a corrupted table won't
be detected until the next save; including the ITS not working as expected
after the restore.  As an example, if the guest sets tables overlapping
each other, which would most likely result in some corrupted table, this is
what we would see from the host point of view:

	guest sets base addresses that overlap each other
	save ioctl
	restore ioctl
	save ioctl (fails)

Ideally, we would like the first save to fail, but overlapping tables could
actually be intended by the guest. So, let's at least fail on the restore
with some checks: like checking that device and event IDs don't overflow
their tables.

Signed-off-by: Ricardo Koller &lt;ricarkol@google.com&gt;
Reviewed-by: Oliver Upton &lt;oupton@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20220510001633.552496-3-ricarkol@google.com
</content>
</entry>
<entry>
<title>KVM: arm64: vgic: Check that new ITEs could be saved in guest memory</title>
<updated>2022-05-16T12:58:04Z</updated>
<author>
<name>Ricardo Koller</name>
<email>ricarkol@google.com</email>
</author>
<published>2022-05-10T00:16:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cafe7e544d4979da222eaff12141ecac07901b9c'/>
<id>urn:sha1:cafe7e544d4979da222eaff12141ecac07901b9c</id>
<content type='text'>
Try to improve the predictability of ITS save/restores by failing
commands that would lead to failed saves. More specifically, fail any
command that adds an entry into an ITS table that is not in guest
memory, which would otherwise lead to a failed ITS save ioctl. There
are already checks for collection and device entries, but not for
ITEs.  Add the corresponding check for the ITT when adding ITEs.

Reviewed-by: Eric Auger &lt;eric.auger@redhat.com&gt;
Signed-off-by: Ricardo Koller &lt;ricarkol@google.com&gt;
Reviewed-by: Oliver Upton &lt;oupton@google.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20220510001633.552496-2-ricarkol@google.com
</content>
</entry>
<entry>
<title>KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround</title>
<updated>2022-05-15T10:18:50Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-05-14T10:25:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cae889302ebf5a9b22ca3580996118b8d20b3ae6'/>
<id>urn:sha1:cae889302ebf5a9b22ca3580996118b8d20b3ae6</id>
<content type='text'>
Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
original M1 and generate random SErrors in the host when a guest
tickles the GICv3 CPU interface the wrong way.

Add the part numbers for both the CPU types found in these two
new implementations, and add them to the hall of shame. This also
applies to the Ultra version, as it is composed of 2 Max SoCs.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Link: https://lore.kernel.org/r/20220514102524.3188730-1-maz@kernel.org
</content>
</entry>
</feed>
