Linux kernel development work - see feature branches https://git.zx2c4.com/linux-dev/atom/arch/loongarch/include/asm/pgtable.h?h=linus%2Fmaster 2022-06-03T12:09:29Z 2022-06-03T12:09:29Z Huacai Chen chenhuacai@loongson.cn 2022-05-31T10:04:12Z urn:sha1:d4b6f1562a3c3284adcef81d6e4f183d7d34b8a9 Add Non-Uniform Memory Access (NUMA) support for LoongArch. LoongArch has 48-bit physical address, but the HyperTransport I/O bus only support 40-bit address, so we need a custom phys_to_dma() and dma_to_phys() to extract the 4-bit node id (bit 44~47) from Loongson-3's 48-bit physical address space and embed it into 40-bit. In the 40-bit dma address, node id offset can be read from the LS7A_DMA_CFG register. Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2022-06-03T12:09:29Z Huacai Chen chenhuacai@loongson.cn 2022-05-31T10:04:12Z urn:sha1:46859ac8af52ae599e1b51992ddef3eb43f295fc LoongArch-based procesors have 4, 8 or 16 cores per package. This patch adds multi-processor (SMP) support for LoongArch. Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> 2022-06-03T12:09:28Z Huacai Chen chenhuacai@loongson.cn 2022-05-31T10:04:11Z urn:sha1:09cfefb7fa70c3af011b0db0a513fd80b2f18abc Add memory management support for LoongArch, including: cache and tlb management, page fault handling and ioremap/mmap support. Reviewed-by: WANG Xuerui <git@xen0n.name> Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>