<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/loongarch/pci, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/loongarch/pci?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/loongarch/pci?h=master'/>
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<updated>2022-10-12T08:36:14Z</updated>
<entry>
<title>LoongArch: Use TLB for ioremap()</title>
<updated>2022-10-12T08:36:14Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhuacai@loongson.cn</email>
</author>
<published>2022-10-12T08:36:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d279134168c78ac2caa1f7cd2a846579da1c93ac'/>
<id>urn:sha1:d279134168c78ac2caa1f7cd2a846579da1c93ac</id>
<content type='text'>
We can support more cache attributes (e.g., CC, SUC and WUC) and page
protection when we use TLB for ioremap(). The implementation is based
on GENERIC_IOREMAP.

The existing simple ioremap() implementation has better performance so
we keep it and introduce ARCH_IOREMAP to control the selection.

We move pagetable_init() earlier to make early ioremap() works, and we
modify the PCI ecam mapping because the TLB-based version of ioremap()
will actually take the size into account.

Signed-off-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
</content>
</entry>
<entry>
<title>LoongArch: Refactor cache probe and flush methods</title>
<updated>2022-10-12T08:36:14Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhuacai@loongson.cn</email>
</author>
<published>2022-10-12T08:36:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b61a40afca164a9bd066f749beff3bf209c5e209'/>
<id>urn:sha1:b61a40afca164a9bd066f749beff3bf209c5e209</id>
<content type='text'>
Current cache probe and flush methods have some drawbacks:
1, Assume there are 3 cache levels and only 3 levels;
2, Assume L1 = I + D, L2 = V, L3 = S, V is exclusive, S is inclusive.

However, the fact is I + D, I + D + V, I + D + S and I + D + V + S are
all valid. So, refactor the cache probe and flush methods to adapt more
types of cache hierarchy.

Signed-off-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
</content>
</entry>
<entry>
<title>LoongArch: Add PCI controller support</title>
<updated>2022-08-12T05:10:11Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhuacai@loongson.cn</email>
</author>
<published>2022-08-06T07:19:33Z</published>
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<id>urn:sha1:57fc7323a8e7c2e7c1d5795ab63cb3ffea3cfdfb</id>
<content type='text'>
Loongson64 based systems are PC-like systems which use PCI/PCIe as its
I/O bus, This patch adds the PCI host controller support for LoongArch.

Reviewed-by: WANG Xuerui &lt;git@xen0n.name&gt;
Signed-off-by: Jianmin Lv &lt;lvjianmin@loongson.cn&gt;
Signed-off-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
</content>
</entry>
<entry>
<title>LoongArch: Add build infrastructure</title>
<updated>2022-06-03T12:09:27Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhuacai@loongson.cn</email>
</author>
<published>2022-05-31T10:04:11Z</published>
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<id>urn:sha1:fa96b57c149061f71a70bd6582d995f6424fbbf4</id>
<content type='text'>
Add Kbuild, Makefile, Kconfig and link script for LoongArch build
infrastructure.

Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: WANG Xuerui &lt;git@xen0n.name&gt;
Reviewed-by: Jiaxun Yang &lt;jiaxun.yang@flygoat.com&gt;
Signed-off-by: Huacai Chen &lt;chenhuacai@loongson.cn&gt;
</content>
</entry>
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