linux-dev/arch/mips/include/asm/mach-cavium-octeon, branch master

MIPS: Remove TX39XX support

2022-03-01T09:07:22Z

No (active) developer owns this hardware, so let's remove Linux support. Signed-off-by: Thomas Bogendoerfer Acked-by: Guenter Roeck Reviewed-by: Geert Uytterhoeven Tested-by: Geert Uytterhoeven Acked-by: Atsushi Nemoto

MIPS: Loongson64: Add kexec/kdump support

2021-04-16T07:18:06Z

Add kexec/kdump support for Loongson64 by: 1, Provide Loongson-specific kexec functions: loongson_kexec_prepare(), loongson_kexec_shutdown() and loongson_crash_shutdown(); 2, Provide Loongson-specific assembly code in kexec_smp_wait(); To start Loongson64, The boot CPU needs 3 parameters: fw_arg0: the number of arguments in cmdline (i.e., argc). fw_arg1: structure holds cmdline such as "root=/dev/sda1 console=tty" (i.e., argv). fw_arg2: environment (i.e., envp, additional boot parameters from LEFI). Non-boot CPUs do not need one parameter as the IPI mailbox base address. They query their own IPI mailbox to get PC, SP and GP in a loopi, until the boot CPU brings them up. loongson_kexec_prepare(): Setup cmdline for kexec/kdump. The kexec/kdump cmdline comes from kexec's "append" option string. This structure will be parsed in fw_init_cmdline() of arch/mips/fw/lib/cmdline.c. Both image ->control_code_page and the cmdline need to be in a safe memory region (memory allocated by the old kernel may be corrupted by the new kernel). In order to maintain compatibility for the old firmware, the low 2MB is reserverd and safe for Loongson. So let KEXEC_CTRL_CODE and KEXEC_ARGV_ ADDR be here. LEFI parameters may be corrupted at runtime, so backup it at mips_reboot_setup(), and then restore it at loongson_kexec_shutdown() /loongson_crash_shutdown(). loongson_kexec_shutdown(): Wake up all present CPUs and let them go to reboot_code_buffer. Pass the kexec parameters to kexec_args. loongson_crash_shutdown(): Pass the kdump parameters to kexec_args. The assembly part in kexec_smp_wait provide a routine as BIOS does, in order to keep secondary CPUs in a querying loop. The layout of low 2MB memory in our design: 0x80000000, the first MB, the first 64K, Exception vectors 0x80010000, the first MB, the second 64K, STR (suspend) data 0x80020000, the first MB, the third and fourth 64K, UEFI HOB 0x80040000, the first MB, the fifth 64K, RT-Thread for SMC 0x80100000, the second MB, the first 64K, KEXEC code 0x80108000, the second MB, the second 64K, KEXEC data Cc: Eric Biederman Tested-by: Jinyang He Signed-off-by: Huacai Chen Signed-off-by: Jinyang He Signed-off-by: Youling Tang Signed-off-by: Thomas Bogendoerfer

MIPS: Remove mach-*/war.h

2020-09-07T20:25:27Z

After conversion of all WAR defines we can now remove all mach-*/war.h files. Signed-off-by: Thomas Bogendoerfer

MIPS: Get rid of CAVIUM_OCTEON_DCACHE_PREFETCH_WAR

2020-09-07T20:25:16Z

CAVIUM_OCTEON_DCACHE_PREFETCH_WAR is a check for Octeon model CN6XXXX. By using the version check we can remove the define. Signed-off-by: Thomas Bogendoerfer

MIPS: Get rid of BCM1250_M3_WAR

2020-09-07T20:25:03Z

BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS. So using this option directly lets and remove define. Signed-off-by: Thomas Bogendoerfer

MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS

2020-09-07T20:24:51Z

SB1250 uart bug is related to PASS 2 workarounds. Use config CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR. Signed-off-by: Thomas Bogendoerfer

MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option

2020-09-07T20:24:40Z

Use a new config option to enable MIPS 34K ITLB workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer

MIPS: Convert R10000_LLSC_WAR info a config option

2020-09-07T20:24:27Z

Use a new config option to enabel R1000_LLSC workaound and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer

MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option

2020-09-07T20:24:19Z

Use a new config option to enable I-cache refill workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer

MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option

2020-09-07T20:24:09Z

Use a new config option to enable TX49XX I-cache index invalidate workaround and remove define from different war.h files. Signed-off-by: Thomas Bogendoerfer