linux-dev/arch/mips/include/asm/mach-rm, branch masterLinux kernel development work - see feature brancheshttps://git.zx2c4.com/linux-dev/atom/arch/mips/include/asm/mach-rm?h=master2020-09-07T20:25:27ZMIPS: Remove mach-*/war.h2020-09-07T20:25:27ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:54Zurn:sha1:601637e42df045ca2d1a9324d56765f044d46866
After conversion of all WAR defines we can now remove all mach-*/war.h
files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Get rid of BCM1250_M3_WAR2020-09-07T20:25:03ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:52Zurn:sha1:ab5743079b8e3d3d4309664903f6b1f579168a56
BCM1250_M3_WAR is depending on CONFIG_CONFIG_SB1_PASS_2_WORKAROUNDS.
So using this option directly lets and remove define.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Replace SIBYTE_1956_WAR by CONFIG_SB1_PASS_2_WORKAROUNDS2020-09-07T20:24:51ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:51Zurn:sha1:43df4eb2fc9511e09c66252c3fec4f8933a77c73
SB1250 uart bug is related to PASS 2 workarounds. Use config
CONFIG_SB1_PASS_2_WORKAROUNDS directly and get rid of SIBYTE_1956_WAR.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Convert MIPS34K_MISSED_ITLB_WAR into a config option2020-09-07T20:24:40ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:50Zurn:sha1:a7fbed988f31d3bf92415226fdf2ffd54606ad93
Use a new config option to enable MIPS 34K ITLB workaround and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Convert R10000_LLSC_WAR info a config option2020-09-07T20:24:27ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:49Zurn:sha1:256ec489f1c7726f0db9ffee88ba7cdc317806cd
Use a new config option to enabel R1000_LLSC workaound and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Convert ICACHE_REFILLS_WORKAROUND_WAR into a config option2020-09-07T20:24:19ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:48Zurn:sha1:886ee1363a3ad2b890959f07cffe8d91d995b93a
Use a new config option to enable I-cache refill workaround and remove
define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Convert TX49XX_ICACHE_INDEX_INV into a config option2020-09-07T20:24:09ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:47Zurn:sha1:24a1c023f3ff3082fee9c019c17e6a34e2ddfe6b
Use a new config option to enable TX49XX I-cache index invalidate
workaround and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Remove MIPS4K_ICACHE_REFILL_WAR and MIPS_CACHE_SYNC_WAR2020-09-07T20:24:01ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:46Zurn:sha1:142439b0520a239bc10cf6c87d7773644c5dfe04
Neither MIPS4K_ICACHE_REFILL_WAR nor MIPS_CACHE_SYNC_WAR are implemented,
so removing defines for it won't change anything.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Convert R4600_V2_HIT_CACHEOP into a config option2020-09-07T20:23:48ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:45Zurn:sha1:44def3426e4ac5a2dbdb5c8304397f4daa38eb2f
Use a new config option to enable R4600 V2 cacheop hit workaround
and remove define from different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
MIPS: Convert R4600_V1_HIT_CACHEOP into a config option2020-09-07T20:23:38ZThomas Bogendoerfertsbogend@alpha.franken.de2020-08-24T16:32:44Zurn:sha1:5e5b6527128cea50f12a7064bf61b130b3a2739a
Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>