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<title>linux-dev/arch/mips/loongson/Makefile, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/mips/loongson/Makefile?h=master</id>
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<updated>2015-06-21T19:53:59Z</updated>
<entry>
<title>MIPS: Loongson: Naming style cleanup and rework</title>
<updated>2015-06-21T19:53:59Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhc@lemote.com</email>
</author>
<published>2015-04-21T02:00:35Z</published>
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<id>urn:sha1:30ad29bb48881ee11f5daf30c6fc50292ae08c57</id>
<content type='text'>
Currently, code of Loongson-2/3 is under loongson directory and code of
Loongson-1 is under loongson1 directory. Besides, there are Kconfig
options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is
very ugly and confusing. Since Loongson-2/3 are both 64-bit general-
purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names
and Kconfig symbols from loongson/loongson1 to loongson64/loongson32.

[ralf@linux-mips.org: Resolve a number of simple conflicts.]

Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Cc: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang &lt;zhangfx@lemote.com&gt;
Cc: Zhangjin Wu &lt;wuzhangjin@gmail.com&gt;
Cc: Kelvin Cheung &lt;keguang.zhang@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/9790/
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Loongson 3: Add IRQ init and dispatch support</title>
<updated>2014-03-31T16:17:12Z</updated>
<author>
<name>Huacai Chen</name>
<email>chenhc@lemote.com</email>
</author>
<published>2014-03-21T10:44:04Z</published>
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<id>urn:sha1:d788bfa900748f3325894d18a763d1ba42326c28</id>
<content type='text'>
IRQ routing path of Loongson-3:
Devices(most) --&gt; I8259 --&gt; HT Controller --&gt; IRQ Routing Table --&gt; CPU
                                                  ^
                                                  |
Device(legacy devices such as UART) --&gt; Bonito ---|

IRQ Routing Table route 32 INTs to CPU's INT0~INT3(IP2~IP5 of CP0), 32
INTs include 16 HT INTs(mostly), 4 PCI INTs, 1 LPC INT, etc. IP6 is used
for IPI and IP7 is used for internal MIPS timer. LOONGSON_INT_ROUTER_*
are IRQ Routing Table registers.

I8259 IRQs are 1:1 mapped to HT1 INTs. LOONGSON_HT1_* are configuration
registers of HT1 controller.

Signed-off-by: Huacai Chen &lt;chenhc@lemote.com&gt;
Signed-off-by: Hongliang Tao &lt;taohl@lemote.com&gt;
Signed-off-by: Hua Yan &lt;yanh@lemote.com&gt;
Tested-by: Alex Smith &lt;alex.smith@imgtec.com&gt;
Reviewed-by: Alex Smith &lt;alex.smith@imgtec.com&gt;
Cc: John Crispin &lt;john@phrozen.org&gt;
Cc: Steven J. Hill &lt;Steven.Hill@imgtec.com&gt;
Cc: Aurelien Jarno &lt;aurelien@aurel32.net&gt;
Cc: linux-mips@linux-mips.org
Cc: Fuxin Zhang &lt;zhangfx@lemote.com&gt;
Cc: Zhangjin Wu &lt;wuzhangjin@gmail.com&gt;
Patchwork: https://patchwork.linux-mips.org/patch/6634
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Whitespace cleanup.</title>
<updated>2013-02-01T09:00:22Z</updated>
<author>
<name>Ralf Baechle</name>
<email>ralf@linux-mips.org</email>
</author>
<published>2013-01-22T11:59:30Z</published>
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<id>urn:sha1:7034228792cc561e79ff8600f02884bd4c80e287</id>
<content type='text'>
Having received another series of whitespace patches I decided to do this
once and for all rather than dealing with this kind of patches trickling
in forever.

Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Lemote 2F: Add IRQ support</title>
<updated>2009-12-17T01:57:13Z</updated>
<author>
<name>Wu Zhangjin</name>
<email>wuzhangjin@gmail.com</email>
</author>
<published>2009-11-09T16:06:14Z</published>
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<id>urn:sha1:6616db78eecab1236781c546670391e1e5dff256</id>
<content type='text'>
The generic i8259_irq() will make kernel hang on booting, so Loongson 2F
needs its own polling method.

IP6 is shared by the bonito interrupt and perfcounter interrupts.

Signed-off-by: Wu Zhangjin &lt;wuzhangjin@gmail.com&gt;
Cc: zhangfx@lemote.com
Cc: yanh@lemote.com 
Cc: huhb@lemote.com
Cc: Nicholas Mc Guire &lt;hofrat@hofr.at&gt;
Cc: Arnaud Patard &lt;apatard@mandriva.com&gt;
Cc: loongson-dev@googlegroups.com
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
<entry>
<title>MIPS: Loongson: Split common loongson source code out</title>
<updated>2009-09-17T18:07:47Z</updated>
<author>
<name>Wu Zhangjin</name>
<email>wuzhangjin@gmail.com</email>
</author>
<published>2009-07-02T15:26:45Z</published>
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<id>urn:sha1:85749d24bcf90440b10394312e5b1c96d1a62cdb</id>
<content type='text'>
To share common loongson source code between all of the loongson-based
machines. there is a need to split it out of the fuloong-2e/ directory.
at the same time, other according tuning is needed. the machine-specific
parts are defined as macros in relative header file, pci.h, mem.h,
machine.h.

Signed-off-by: Wu Zhangjin &lt;wuzhangjin@gmail.com&gt;
Signed-off-by: Ralf Baechle &lt;ralf@linux-mips.org&gt;
</content>
</entry>
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