linux-dev/arch/mips/loongson/common/platform.c, branch master

MIPS: Loongson: Naming style cleanup and rework

2015-06-21T19:53:59Z

Currently, code of Loongson-2/3 is under loongson directory and code of Loongson-1 is under loongson1 directory. Besides, there are Kconfig options such as MACH_LOONGSON and MACH_LOONGSON1. This naming style is very ugly and confusing. Since Loongson-2/3 are both 64-bit general- purpose CPU while Loongson-1 is 32-bit SoC, we rename both file names and Kconfig symbols from loongson/loongson1 to loongson64/loongson32. [ralf@linux-mips.org: Resolve a number of simple conflicts.] Signed-off-by: Huacai Chen Cc: Steven J. Hill Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang Cc: Zhangjin Wu Cc: Kelvin Cheung Patchwork: https://patchwork.linux-mips.org/patch/9790/ Signed-off-by: Ralf Baechle

MIPS: Whitespace cleanup.

2013-02-01T09:00:22Z

Having received another series of whitespace patches I decided to do this once and for all rather than dealing with this kind of patches trickling in forever. Signed-off-by: Ralf Baechle

mips: fix implicit smp.h usage in various files.

2011-10-31T23:30:55Z

We need to call out inclusion of smp.h, or with the module.h cleanup we'll get things like: arch/mips/loongson/common/platform.c:21: error: implicit declaration of function 'smp_processor_id' arch/mips/vr41xx/common/giu.c:84: error: implicit declaration of function 'smp_processor_id' arch/mips/vr41xx/common/rtc.c:85: error: implicit declaration of function 'smp_processor_id' Signed-off-by: Paul Gortmaker

MIPS: Loongson: Change the Email address of Wu Zhangjin

2010-02-27T11:53:12Z

Currently wuzj@lemote.com is not usable; change it to wuzhangjin@gmail.com. Signed-off-by: Wu Zhangjin Cc: linux-mips@linux-mips.org Cc: yanh@lemote.com Cc: huhb@lemote.com Cc: zhangfx@lemote.com Patchwork: http://patchwork.linux-mips.org/patch/829/ Signed-off-by: Ralf Baechle

MIPS: Loongson 2F: Add CPU frequency scaling support

2009-12-17T01:57:20Z

Loongson 2F supports CPU clock scaling. When put it into wait mode by setting the frequency as ZERO it will stay in this mode until an external interrupt wakes the CPU again. To enable clock scaling support, an external timer of a known stable rate is required. Signed-off-by: Wu Zhangjin Cc: linux-mips@linux-mips.org Cc: cpufreq@vger.kernel.org, Cc: Dave Jones , Cc: Dominik Brodowski , Cc: yanh@lemote.com Cc: huhb@lemote.com, Patchwork: http://patchwork.linux-mips.org/patch/660/ Patchwork: http://patchwork.linux-mips.org/patch/751/ Signed-off-by: Ralf Baechle