linux-dev/arch/mips/mti-malta, branch master

mips: mti-malta: Fix refcount leak in malta-time.c

2022-06-21T15:04:30Z

In update_gic_frequency_dt(), of_find_compatible_node() will return a node pointer with refcount incremented. We should use of_node_put() when it is not used anymore. Signed-off-by: Liang He Signed-off-by: Thomas Bogendoerfer

MIPS: Remove redundant definitions of device_tree_init()

2022-03-14T14:09:02Z

There exists many same definitions of device_tree_init() for various platforms, add a weak function in arch/mips/kernel/prom.c to clean up the related code. Signed-off-by: Tiezhu Yang Signed-off-by: Thomas Bogendoerfer

Merge tag 'mips_5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2021-09-03T18:11:54Z

Pull MIPS updates from Thomas Bogendoerfer: - converted Pistachio platform to use MIPS generic kernel - fixes and cleanups * tag 'mips_5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (29 commits) MIPS: Malta: fix alignment of the devicetree buffer MIPS: ingenic: Unconditionally enable clock of CPU #0 MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports MIPS: mscc: ocelot: disable all switch ports by default MAINTAINERS: adjust PISTACHIO SOC SUPPORT after its retirement MIPS: Return true/false (not 1/0) from bool functions MIPS: generic: Return true/false (not 1/0) from bool functions MIPS: Make a alias for pistachio_defconfig MIPS: Retire MACH_PISTACHIO MIPS: config: generic: Add config for Marduk board pinctrl: pistachio: Make it as an option phy: pistachio-usb: Depend on MIPS || COMPILE_TEST clocksource/drivers/pistachio: Make it selectable for MIPS clk: pistachio: Make it selectable for generic MIPS kernel MIPS: DTS: Pistachio add missing cpc and cdmm MIPS: generic: Allow generating FIT image for Marduk board MIPS: locking/atomic: Fix atomic{_64,}_sub_if_positive MIPS: loongson2ef: don't build serial.o unconditionally MIPS: Replace deprecated CPU-hotplug functions. MIPS: Alchemy: Fix spelling contraction "cant" -> "can't" ...

MIPS: Malta: fix alignment of the devicetree buffer

2021-09-02T08:18:26Z

Starting with following patch MIPS Malta is not able to boot: | commit 79edff12060fe7772af08607eff50c0e2486c5ba | Author: Rob Herring | scripts/dtc: Update to upstream version v1.6.0-51-g183df9e9c2b9 The reason is the alignment test added to the fdt_ro_probe_(). To fix this issue, we need to make sure that fdt_buf is aligned. Since the dtc patch was designed to uncover potential issue, I handle initial MIPS Malta patch as initial bug. Fixes: e81a8c7dabac ("MIPS: Malta: Setup RAM regions via DT") Signed-off-by: Oleksij Rempel Signed-off-by: Thomas Bogendoerfer

MIPS: Malta: Do not byte-swap accesses to the CBUS UART

2021-07-21T10:52:14Z

Correct big-endian accesses to the CBUS UART, a Malta on-board discrete TI16C550C part wired directly to the system controller's device bus, and do not use byte swapping with the 32-bit accesses to the device. The CBUS is used for devices such as the boot flash memory needed early on in system bootstrap even before PCI has been initialised. Therefore it uses the system controller's device bus, which follows the endianness set with the CPU, which means no byte-swapping is ever required for data accesses to CBUS, unlike with PCI. The CBUS UART uses the UPIO_MEM32 access method, that is the `readl' and `writel' MMIO accessors, which on the MIPS platform imply byte-swapping with PCI systems. Consequently the wrong byte lane is accessed with the big-endian configuration and the UART is not correctly accessed. As it happens the UPIO_MEM32BE access method makes use of the `ioread32' and `iowrite32' MMIO accessors, which still use `readl' and `writel' respectively, however they byte-swap data passed, effectively cancelling swapping done with the accessors themselves and making it suitable for the CBUS UART. Make the CBUS UART switch between UPIO_MEM32 and UPIO_MEM32BE then, based on the endianness selected. With this change in place the device is correctly recognised with big-endian Malta at boot, along with the Super I/O devices behind PCI: Serial: 8250/16550 driver, 5 ports, IRQ sharing enabled printk: console [ttyS0] disabled serial8250.0: ttyS0 at I/O 0x3f8 (irq = 4, base_baud = 115200) is a 16550A printk: console [ttyS0] enabled printk: bootconsole [uart8250] disabled serial8250.0: ttyS1 at I/O 0x2f8 (irq = 3, base_baud = 115200) is a 16550A serial8250.0: ttyS2 at MMIO 0x1f000900 (irq = 20, base_baud = 230400) is a 16550A Fixes: e7c4782f92fc ("[MIPS] Put an end to 's long and annyoing existence") Cc: stable@vger.kernel.org # v2.6.23+ Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Maciej W. Rozycki Link: https://lore.kernel.org/r/alpine.DEB.2.21.2106260524430.37803@angie.orcam.me.uk Signed-off-by: Greg Kroah-Hartman

MIPS: Malta: Enable magic multipliers for Super I/O UARTs

2021-06-16T07:20:29Z

The SMSC FDC37M817 Super I/O chip has a configuration feature that lets it support special UART divisor values of 32770 and 32769 for bit rates of 230400 and 460800 bits per second respectively. Our 8250 driver core provides support for these special divisors via the UPF_MAGIC_MULTIPLIER flag, and YAMON firmware unconditionally configures the Super I/O chip with these divisors enabled as well, so all we need to do in platform setup for these bit rates to work is to set the flag. Signed-off-by: Maciej W. Rozycki Link: https://lore.kernel.org/r/alpine.DEB.2.21.2105182249380.3032@angie.orcam.me.uk Signed-off-by: Greg Kroah-Hartman

MIPS: Remove KVM_GUEST support

2021-03-10T14:18:40Z

KVM_GUEST is broken and unmaintained, so let's remove it. Reviewed-by: Huacai Chen Reviewed-by: Jiaxun Yang Signed-off-by: Thomas Bogendoerfer

driver core: lift dma_default_coherent into common code

2021-02-13T08:51:45Z

Lift the dma_default_coherent variable from the mips architecture code to the driver core. This allows an architecture to sdefault all device to be DMA coherent at run time, even if the kernel is build with support for DMA noncoherent device. By allowing device_initialize to set the ->dma_coherent field to this default the amount of arch hooks required for this behavior can be greatly reduced. Signed-off-by: Christoph Hellwig Acked-by: Greg Kroah-Hartman Signed-off-by: Thomas Bogendoerfer

MIPS: refactor the runtime coherent vs noncoherent DMA indicators

2021-02-13T08:51:45Z

Replace the global coherentio enum, and the hw_coherentio (fake) boolean variables with a single boolean dma_default_coherent flag. Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Bogendoerfer

MIPS/malta: simplify plat_setup_iocoherency

2021-02-13T08:51:45Z

Given that plat_mem_setup runs before earlyparams are handled and malta selects CONFIG_DMA_MAYBE_COHERENT, coherentio can only be set to IO_COHERENCE_DEFAULT at this point. So remove the checking for other options and merge plat_enable_iocoherency into plat_setup_iocoherency to simplify the code a bit. Signed-off-by: Christoph Hellwig Signed-off-by: Thomas Bogendoerfer