linux-dev/arch/mips/ralink/Kconfig, branch master

mips: dts: ralink: add MT7621 SoC

2022-03-16T14:10:23Z

The MT7621 system-on-a-chip includes an 880 MHz MIPS1004Kc dual-core CPU, a 5-port 10/100/1000 switch/PHY and one RGMII. Add the devicetrees for GB-PC1 and GB-PC2 devices which use MT7621 SoC. Acked-by: Sergio Paracuellos Acked-by: Thomas Bogendoerfer Signed-off-by: Arınç ÜNAL Link: https://lore.kernel.org/r/20220315160149.3617-1-arinc.unal@arinc9.com Signed-off-by: Greg Kroah-Hartman

PCI: mt7621: Add MediaTek MT7621 PCIe host controller driver

2021-10-21T15:59:18Z

Add driver for the PCIe controller of the MT7621 SoC. [bhelgaas: rename from pci-mt7621.c to pcie-mt7621.c; also rename Kconfig symbol from PCI_MT7621 to PCIE_MT7621] Link: https://lore.kernel.org/r/20210922050035.18162-3-sergio.paracuellos@gmail.com Signed-off-by: Sergio Paracuellos Signed-off-by: Lorenzo Pieralisi Signed-off-by: Bjorn Helgaas Acked-by: Greg Kroah-Hartman

mips: ralink: convert to CONFIG_COMMON_CLK

2021-06-08T15:00:09Z

ralink only has a very trivial clock implementation, with everything being fixed clocks. Convert it to CONFIG_COMMON_CLK to reduce the number of platforms that rely on legacy clocks. Of course, the clocks really should be read from the device tree instead, but this is a step into that direction. This adds about 50KB to the kernel image size, which is an unfortunate increase, but not as bad as I had feared: text data bss dec hex filename 3778560 1582216 92256 5453032 5334e8 vmlinux-vocore-before 3822148 1601192 92304 5515644 54297c vmlinux-vocore-after 3870226 1644468 200192 5714886 5733c6 vmlinux-rt305x-before 3916727 1668404 200240 5785371 58471b vmlinux-rt305x-after Signed-off-by: Arnd Bergmann

MIPS: ralink: rt288x: select MIPS_AUTO_PFN_OFFSET

2021-04-06T13:12:58Z

RT288X systems may have a non-zero ramstart causing problems with memory reservations and boot hangs, as well as messages like: Wasting 1048576 bytes for tracking 32768 unused pages Both are alleviated by selecting MIPS_AUTO_PFN_OFFSET for such platforms. Tested on a Belkin F5D8235 v1 RT2880 device. Link: https://lore.kernel.org/linux-mips/20180820233111.xww5232dxbuouf4n@pburton-laptop/ Signed-off-by: Ilya Lipnitskiy Cc: Mike Rapoport Signed-off-by: Thomas Bogendoerfer

clk: Allow the common clk framework to be selectable

2020-05-05T19:34:11Z

Enable build testing and configuration control of the common clk framework so that more code coverage and testing can be done on the common clk framework across various architectures. This also nicely removes the requirement that architectures must select the framework when they don't use it in architecture code. There's one snag with doing this, and that's making sure that randconfig builds don't select this option when some architecture or platform implements 'struct clk' outside of the common clk framework. Introduce a new config option 'HAVE_LEGACY_CLK' to indicate those platforms that haven't migrated to the common clk framework and therefore shouldn't be allowed to select this new config option. Also add a note that we hope one day to remove this config entirely. Based on a patch by Mark Brown . Cc: Mark Brown Cc: Geert Uytterhoeven Cc: Mark Salter Cc: Aurelien Jacquiot Cc: Jiaxun Yang Cc: Guan Xuetao Cc: Russell King Cc: Arnd Bergmann Cc: Yoshinori Sato Cc: Rich Felker Cc: Thomas Bogendoerfer Cc: Cc: Cc: Cc: Cc: Link: https://lore.kernel.org/r/1470915049-15249-1-git-send-email-broonie@kernel.org Signed-off-by: Stephen Boyd Link: https://lkml.kernel.org/r/20200409064416.83340-8-sboyd@kernel.org Reviewed-by: Mark Brown Reviewed-by: Arnd Bergmann

MIPS: ralink: mt7621: Fix soc_device introduction

2020-03-28T16:26:36Z

Depending on selected SMP config options soc_device didn't get initialised at all. With UP config vmlinux didn't link because of missing soc bus. Fixes: 71b9b5e0130d ("MIPS: ralink: mt7621: introduce 'soc_device' initialization") Signed-off-by: Thomas Bogendoerfer Tested-by: René van Dorst

MIPS: ralink: enable PCI support only if driver for mt7621 SoC is selected

2019-11-14T05:09:37Z

Some versions of SoC MT7621 have three PCI express hosts. Some boards make use of those PCI through the staging driver mt7621-pci. Recently PCI support has been removed from MT7621 Soc kernel configuration due to a build error. This makes imposible to compile staging driver and produces a regression for gnubee based boards. Enable support for PCI again but enable it only if staging mt7621-pci driver is selected. Fixes: c4d48cf5e2f0 ("MIPS: ralink: deactivate PCI support for SOC_MT7621") Cc: Hauke Mehrtens Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: john@phrozen.org Cc: NeilBrown Cc: linux-mips@vger.kernel.org Signed-off-by: Sergio Paracuellos Link: https://lore.kernel.org/r/20191019081233.7337-1-sergio.paracuellos@gmail.com Signed-off-by: Greg Kroah-Hartman

MIPS: ralink: deactivate PCI support for SOC_MT7621

2019-09-06T15:45:03Z

The Linux does not support PCI on the SOC_MT7621, if it is selected the Linux build runs into a compile error. Remove HAVE_PCI from the SOC_MT7621 SoC. Signed-off-by: Hauke Mehrtens Signed-off-by: Paul Burton Cc: ralf@linux-mips.org Cc: jhogan@kernel.org Cc: john@phrozen.org Cc: linux-mips@vger.kernel.org

Merge tag 'mips_fixes_4.21_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

2019-01-05T20:48:25Z

Pull MIPS fixes from Paul Burton: "A few early MIPS fixes for 4.21: - The Broadcom BCM63xx platform sees a fix for resetting the BCM6368 ethernet switch, and the removal of a platform device we've never had a driver for. - The Alchemy platform sees a few fixes for bitrot that occurred within the past few cycles. - We now enable vectored interrupt support for the MediaTek MT7620 SoC, which makes sense since they're supported by the SoC but in this case also works around a bug relating to the location of exception vectors when using a recent version of U-Boot. - The atomic64_fetch_*_relaxed() family of functions see a fix for a regression in MIPS64 kernels since v4.19. - Cavium Octeon III CN7xxx systems will now disable their RGMII interfaces rather than attempt to enable them & warn about the lack of support for doing so, as they did since initial CN7xxx ethernet support was added in v4.7. - The Microsemi/Microchip MSCC SoCs gain a MAINTAINERS entry. - .mailmap now provides consistency for Dengcheng Zhu's name & current email address" * tag 'mips_fixes_4.21_1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: MIPS: OCTEON: mark RGMII interface disabled on OCTEON III MIPS: Fix a R10000_LLSC_WAR logic in atomic.h MIPS: BCM63XX: drop unused and broken DSP platform device mailmap: Update name spelling and email for Dengcheng Zhu MIPS: ralink: Select CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 MAINTAINERS: Add a maintainer for MSCC MIPS SoCs MIPS: Alchemy: update dma masks for devboard devices MIPS: Alchemy: update cpu-feature-overrides MIPS: Alchemy: drop DB1000 IrDA support bits MIPS: alchemy: cpu_all_mask is forbidden for clock event devices MIPS: BCM63XX: fix switch core reset on BCM6368

MIPS: ralink: Select CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8

2018-12-23T16:04:15Z

Testing has shown, that when using mainline U-Boot on MT7688 based boards, the system may hang or crash while mounting the root-fs. The main issue here is that mainline U-Boot configures EBase to a value near the end of system memory. And with CONFIG_CPU_MIPSR2_IRQ_VI disabled, trap_init() will not allocate a new area to place the exception handler. The original value will be used and the handler will be copied to this location, which might already be used by some userspace application. The MT7688 supports VI - its config3 register is 0x00002420, so VInt (Bit 5) is set. But without setting CONFIG_CPU_MIPSR2_IRQ_VI this bit will not be evaluated to result in "cpu_has_vi" being set. This patch now selects CONFIG_CPU_MIPSR2_IRQ_VI on MT7620/8 which results trap_init() to allocate some memory for the exception handler. Please note that this issue was not seen with the Mediatek U-Boot version, as it does not touch EBase (stays at default of 0x8000.0000). This is strictly also not correct as the kernel (_text) resides here. Signed-off-by: Stefan Roese [paul.burton@mips.com: s/beeing/being/] Signed-off-by: Paul Burton Cc: John Crispin Cc: Daniel Schwierzeck Cc: Ralf Baechle Cc: linux-mips@linux-mips.org