linux-dev/arch/mips/ralink/common.h, branch linus/master

MIPS: ralink: mt7621: add memory detection support

2021-03-29T09:18:54Z

mt7621 has the following memory map: 0x0-0x1c000000: lower 448m memory 0x1c000000-0x2000000: peripheral registers 0x20000000-0x2400000: higher 64m memory detect_memory_region in arch/mips/kernel/setup.c only adds the first memory region and isn't suitable for 512m memory detection because it may accidentally read the memory area for peripheral registers. This commit adds memory detection capability for mt7621: 1. Add the highmem area when 512m is detected. 2. Guard memcmp from accessing peripheral registers: This only happens when a user decided to change kernel load address to 256m or higher address. Since this is a quite unusual case, we just skip 512m testing and return 256m as memory size. Signed-off-by: Chuanhong Guo [Minor commit message reword, make mt7621_memory_detect static] Signed-off-by: Ilya Lipnitskiy Signed-off-by: Thomas Bogendoerfer

MIPS: ralink: annotate prom_soc_init() with __init

2021-03-29T09:18:36Z

prom_soc_init is only called from prom_init in arch/mips/ralink/prom.c, which is already annotated with __init, so annotate prom_soc_init with __init too. Signed-off-by: Ilya Lipnitskiy Signed-off-by: Thomas Bogendoerfer

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55Z

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

MIPS: Change my email address

2016-05-13T12:02:18Z

The old address is no longer valid. Use the my new one instead. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/13201/ Signed-off-by: Ralf Baechle

MIPS: ralink: cleanup the soc specific pinmux data

2014-11-24T06:45:24Z

Before we had a pinctrl driver we used a custom OF api. This patch converts the soc specific pinmux data to a new set of structs. We also add some new pinmux setings. Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/8009/ Signed-off-by: Ralf Baechle

MIPS: ralink: Add support for reset-controller API

2013-09-04T16:27:28Z

Add a helper for reseting different devices on the SoC. Signed-off-by: John Crispin Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/5804/ Patchwork: https://patchwork.linux-mips.org/patch/5797/ Signed-off-by: Ralf Baechle

MIPS: ralink: add memory definition to struct ralink_soc_info

2013-05-07T23:19:11Z

Depending on the actual SoC we have a different base address as well as minimum and maximum size for RAM. Add these fields to the per SoC structure. Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/5179/

MIPS: ralink: add uart mask to struct ralink_pinmux

2013-05-07T23:19:09Z

Add a field for the uart muxing mask and set it inside the rt305x setup code. Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/5744/

MIPS: ralink: add pci group to struct ralink_pinmux

2013-05-07T23:19:09Z

This will be used for RT3662/RT3883. Signed-off-by: Gabor Juhos Acked-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/5173/

MIPS: ralink: rename gpio_pinmux to rt_gpio_pinmux

2013-05-07T23:19:08Z

Add proper namespacing to the variable. Signed-off-by: John Crispin Patchwork: http://patchwork.linux-mips.org/patch/5171/