<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/openrisc/mm/Makefile, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/openrisc/mm/Makefile?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/openrisc/mm/Makefile?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2019-05-21T08:50:46Z</updated>
<entry>
<title>treewide: Add SPDX license identifier - Makefile/Kconfig</title>
<updated>2019-05-21T08:50:46Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-19T12:07:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1'/>
<id>urn:sha1:ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1</id>
<content type='text'>
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>openrisc: add cacheflush support to fix icache aliasing</title>
<updated>2017-11-03T05:01:15Z</updated>
<author>
<name>Jan Henrik Weinstock</name>
<email>jan.weinstock@ice.rwth-aachen.de</email>
</author>
<published>2015-11-04T16:26:10Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=4ee93d80ad73980826d582c7c37caa9597822001'/>
<id>urn:sha1:4ee93d80ad73980826d582c7c37caa9597822001</id>
<content type='text'>
On OpenRISC the icache does not snoop data stores.  This can cause
aliasing as reported by Jan. This patch fixes the issue to ensure icache
is properly synchronized when code is written to memory.  It supports both
SMP and UP flushing.

This supports dcache flush as well for architectures that do not support
write-through caches; most OpenRISC implementations do implement
write-through cache however. Dcache flushes are done only on a single
core as OpenRISC dcaches all support snooping of bus stores.

Signed-off-by: Jan Henrik Weinstock &lt;jan.weinstock@ice.rwth-aachen.de&gt;
[shorne@gmail.com: Squashed patches and wrote commit message]
Signed-off-by: Stafford Horne &lt;shorne@gmail.com&gt;
</content>
</entry>
<entry>
<title>OpenRISC: Build infrastructure</title>
<updated>2011-07-22T16:46:30Z</updated>
<author>
<name>Jonas Bonn</name>
<email>jonas@southpole.se</email>
</author>
<published>2011-06-04T18:52:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f8c4a270d9330a2bc179aeef0a22ea1ed288fb50'/>
<id>urn:sha1:f8c4a270d9330a2bc179aeef0a22ea1ed288fb50</id>
<content type='text'>
Signed-off-by: Jonas Bonn &lt;jonas@southpole.se&gt;
Reviewed-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
</feed>
