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<title>linux-dev/arch/powerpc/kernel/cpu_setup_power.c, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/powerpc/kernel/cpu_setup_power.c?h=linus%2Fmaster</id>
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<updated>2021-11-24T10:08:57Z</updated>
<entry>
<title>powerpc/64s: Always set PMU control registers to frozen/disabled when not in use</title>
<updated>2021-11-24T10:08:57Z</updated>
<author>
<name>Nicholas Piggin</name>
<email>npiggin@gmail.com</email>
</author>
<published>2021-11-23T09:51:49Z</published>
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<id>urn:sha1:245ebf8e7380b3d84c0aac37fbfd9306b45a3a7a</id>
<content type='text'>
KVM PMU management code looks for particular frozen/disabled bits in
the PMU registers so it knows whether it must clear them when coming
out of a guest or not. Setting this up helps KVM make these optimisations
without getting confused. Longer term the better approach might be to
move guest/host PMU switching to the perf subsystem.

Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Reviewed-by: Athira Jajeev &lt;atrajeev@linux.vnet.ibm.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20211123095231.1036501-12-npiggin@gmail.com

</content>
</entry>
<entry>
<title>powerpc/64s: Keep AMOR SPR a constant ~0 at runtime</title>
<updated>2021-11-24T10:08:57Z</updated>
<author>
<name>Nicholas Piggin</name>
<email>npiggin@gmail.com</email>
</author>
<published>2021-11-23T09:51:47Z</published>
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<id>urn:sha1:46f9caf1a246a5c0622fa8cc7e673658e925f97e</id>
<content type='text'>
This register controls supervisor SPR modifications, and as such is only
relevant for KVM. KVM always sets AMOR to ~0 on guest entry, and never
restores it coming back out to the host, so it can be kept constant and
avoid the mtSPR in KVM guest entry.

Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Reviewed-by: Fabiano Rosas &lt;farosas@linux.ibm.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20211123095231.1036501-10-npiggin@gmail.com

</content>
</entry>
<entry>
<title>powerpc/perf: MMCR0 control for PMU registers under PMCC=00</title>
<updated>2020-12-03T14:01:29Z</updated>
<author>
<name>Athira Rajeev</name>
<email>atrajeev@linux.vnet.ibm.com</email>
</author>
<published>2020-11-26T16:54:44Z</published>
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<id>urn:sha1:91668ab7db4bcfae332e561df1de2401f3f18553</id>
<content type='text'>
PowerISA v3.1 introduces new control bit (PMCCEXT) for restricting
access to group B PMU registers in problem state when
MMCR0 PMCC=0b00. In problem state and when MMCR0 PMCC=0b00,
setting the Monitor Mode Control Register bit 54 (MMCR0 PMCCEXT),
will restrict read permission on Group B Performance Monitor
Registers (SIER, SIAR, SDAR and MMCR1). When this bit is set to zero,
group B registers will be readable. In other platforms (like power9),
the older behaviour is retained where group B PMU SPRs are readable.

Patch adds support for MMCR0 PMCCEXT bit in power10 by enabling
this bit during boot and during the PMU event enable/disable callback
functions.

Signed-off-by: Athira Rajeev &lt;atrajeev@linux.vnet.ibm.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/1606409684-1589-8-git-send-email-atrajeev@linux.vnet.ibm.com
</content>
</entry>
<entry>
<title>powerpc/64s: Convert some cpu_setup() and cpu_restore() functions to C</title>
<updated>2020-11-19T03:49:56Z</updated>
<author>
<name>Jordan Niethe</name>
<email>jniethe5@gmail.com</email>
</author>
<published>2020-10-14T07:28:37Z</published>
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<id>urn:sha1:344fbab991a568dc33ad90711b489d870e18d26d</id>
<content type='text'>
The only thing keeping the cpu_setup() and cpu_restore() functions
used in the cputable entries for Power7, Power8, Power9 and Power10 in
assembly was cpu_restore() being called before there was a stack in
generic_secondary_smp_init(). Commit ("powerpc/64: Set up a kernel
stack for secondaries before cpu_restore()") means that it is now
possible to use C.

Rewrite the functions in C so they are a little bit easier to read.
This is not changing their functionality.

Signed-off-by: Jordan Niethe &lt;jniethe5@gmail.com&gt;
[mpe: Tweak copyright and authorship notes]
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20201014072837.24539-2-jniethe5@gmail.com
</content>
</entry>
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