<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/powerpc/platforms/powernv/setup.c, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/powerpc/platforms/powernv/setup.c?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/powerpc/platforms/powernv/setup.c?h=linus%2Fmaster'/>
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<updated>2022-05-22T05:58:28Z</updated>
<entry>
<title>powerpc/powernv: Get STF barrier requirements from device-tree</title>
<updated>2022-05-22T05:58:28Z</updated>
<author>
<name>Russell Currey</name>
<email>ruscur@russell.cc</email>
</author>
<published>2022-04-04T10:15:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d2a3c131981d4498571908df95c3c9393a00adf5'/>
<id>urn:sha1:d2a3c131981d4498571908df95c3c9393a00adf5</id>
<content type='text'>
The device-tree property no-need-store-drain-on-priv-state-switch is
equivalent to H_CPU_BEHAV_NO_STF_BARRIER from the
H_CPU_GET_CHARACTERISTICS hcall on pseries.

Since commit 84ed26fd00c5 ("powerpc/security: Add a security feature for
STF barrier") powernv systems with this device-tree property have been
enabling the STF barrier when they have no need for it.  This patch
fixes this by clearing the STF barrier feature on those systems.

Fixes: 84ed26fd00c5 ("powerpc/security: Add a security feature for STF barrier")
Reported-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Russell Currey &lt;ruscur@russell.cc&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20220404101536.104794-2-ruscur@russell.cc

</content>
</entry>
<entry>
<title>powerpc/powernv: Get L1D flush requirements from device-tree</title>
<updated>2022-05-22T05:58:28Z</updated>
<author>
<name>Russell Currey</name>
<email>ruscur@russell.cc</email>
</author>
<published>2022-04-04T10:15:35Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2efee6adb56159288bce9d1ab51fc9056d7007d4'/>
<id>urn:sha1:2efee6adb56159288bce9d1ab51fc9056d7007d4</id>
<content type='text'>
The device-tree properties no-need-l1d-flush-msr-pr-1-to-0 and
no-need-l1d-flush-kernel-on-user-access are the equivalents of
H_CPU_BEHAV_NO_L1D_FLUSH_ENTRY and H_CPU_BEHAV_NO_L1D_FLUSH_UACCESS
from the H_GET_CPU_CHARACTERISTICS hcall on pseries respectively.

In commit d02fa40d759f ("powerpc/powernv: Remove POWER9 PVR version
check for entry and uaccess flushes") the condition for disabling the
L1D flush on kernel entry and user access was changed from any non-P9
CPU to only checking P7 and P8.  Without the appropriate device-tree
checks for newer processors on powernv, these flushes are unnecessarily
enabled on those systems.  This patch corrects this.

Fixes: d02fa40d759f ("powerpc/powernv: Remove POWER9 PVR version check for entry and uaccess flushes")
Reported-by: Joel Stanley &lt;joel@jms.id.au&gt;
Signed-off-by: Russell Currey &lt;ruscur@russell.cc&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20220404101536.104794-1-ruscur@russell.cc

</content>
</entry>
<entry>
<title>powerpc/powernv: Add __init attribute to eligible functions</title>
<updated>2021-12-23T11:33:15Z</updated>
<author>
<name>Nick Child</name>
<email>nick.child@ibm.com</email>
</author>
<published>2021-12-16T22:00:26Z</published>
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<id>urn:sha1:e5913db1ef22817e128f0a794752f7393205e00b</id>
<content type='text'>
Some functions defined in 'arch/powerpc/platforms/powernv' are
deserving of an `__init` macro attribute. These functions are only
called by other initialization functions and therefore should inherit
the attribute.
Also, change function declarations in header files to include `__init`.

Signed-off-by: Nick Child &lt;nick.child@ibm.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20211216220035.605465-12-nick.child@ibm.com
</content>
</entry>
<entry>
<title>powerpc/64s: Move hash MMU support code under CONFIG_PPC_64S_HASH_MMU</title>
<updated>2021-12-09T11:41:13Z</updated>
<author>
<name>Nicholas Piggin</name>
<email>npiggin@gmail.com</email>
</author>
<published>2021-12-01T14:41:52Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=387e220a2e5e630794e1f5219ed6f11e56271c21'/>
<id>urn:sha1:387e220a2e5e630794e1f5219ed6f11e56271c21</id>
<content type='text'>
Compiling out hash support code when CONFIG_PPC_64S_HASH_MMU=n saves
128kB kernel image size (90kB text) on powernv_defconfig minus KVM,
350kB on pseries_defconfig minus KVM, 40kB on a tiny config.

Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
[mpe: Fixup defined(ARCH_HAS_MEMREMAP_COMPAT_ALIGN), which needs CONFIG.
      Fix radix_enabled() use in setup_initial_memory_limit(). Add some
      stubs to reduce number of ifdefs.]
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20211201144153.2456614-18-npiggin@gmail.com
</content>
</entry>
<entry>
<title>powerpc/powernv: Remove POWER9 PVR version check for entry and uaccess flushes</title>
<updated>2021-11-25T00:25:29Z</updated>
<author>
<name>Nicholas Piggin</name>
<email>npiggin@gmail.com</email>
</author>
<published>2021-05-03T13:02:43Z</published>
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<id>urn:sha1:d02fa40d759ff9a53c93b10d8a4b591688982b26</id>
<content type='text'>
These aren't necessarily POWER9 only, and it's not to say some new
vulnerability may not get discovered on other processors for which
we would like the flexibility of having the workaround enabled by
firmware.

Remove the restriction that the workarounds only apply to POWER9.

However POWER7 and POWER8 are not affected, and they may not have
older firmware that does not advertise this, so clear these workarounds
manually.

Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Reviewed-by: Joel Stanley &lt;joel@jms.id.au&gt;
[mpe: Incorporate changes from Nick, reword comment slightly.]
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20210503130243.891868-5-npiggin@gmail.com

</content>
</entry>
<entry>
<title>mm/memory_hotplug: remove CONFIG_MEMORY_HOTPLUG_SPARSE</title>
<updated>2021-11-06T20:30:42Z</updated>
<author>
<name>David Hildenbrand</name>
<email>david@redhat.com</email>
</author>
<published>2021-11-05T20:44:24Z</published>
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<id>urn:sha1:50f9481ed9fb8a2d2a06a155634c7f9eeff9fa61</id>
<content type='text'>
CONFIG_MEMORY_HOTPLUG depends on CONFIG_SPARSEMEM, so there is no need for
CONFIG_MEMORY_HOTPLUG_SPARSE anymore; adjust all instances to use
CONFIG_MEMORY_HOTPLUG and remove CONFIG_MEMORY_HOTPLUG_SPARSE.

Link: https://lkml.kernel.org/r/20210929143600.49379-3-david@redhat.com
Signed-off-by: David Hildenbrand &lt;david@redhat.com&gt;
Acked-by: Shuah Khan &lt;skhan@linuxfoundation.org&gt;	[kselftest]
Acked-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Acked-by: Oscar Salvador &lt;osalvador@suse.de&gt;
Cc: Alex Shi &lt;alexs@kernel.org&gt;
Cc: Andy Lutomirski &lt;luto@kernel.org&gt;
Cc: Benjamin Herrenschmidt &lt;benh@kernel.crashing.org&gt;
Cc: Borislav Petkov &lt;bp@alien8.de&gt;
Cc: Dave Hansen &lt;dave.hansen@linux.intel.com&gt;
Cc: "H. Peter Anvin" &lt;hpa@zytor.com&gt;
Cc: Ingo Molnar &lt;mingo@redhat.com&gt;
Cc: Jason Wang &lt;jasowang@redhat.com&gt;
Cc: Jonathan Corbet &lt;corbet@lwn.net&gt;
Cc: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Cc: "Michael S. Tsirkin" &lt;mst@redhat.com&gt;
Cc: Michal Hocko &lt;mhocko@suse.com&gt;
Cc: Mike Rapoport &lt;rppt@kernel.org&gt;
Cc: Paul Mackerras &lt;paulus@samba.org&gt;
Cc: Peter Zijlstra &lt;peterz@infradead.org&gt;
Cc: "Rafael J. Wysocki" &lt;rafael@kernel.org&gt;
Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Andrew Morton &lt;akpm@linux-foundation.org&gt;
Signed-off-by: Linus Torvalds &lt;torvalds@linux-foundation.org&gt;
</content>
</entry>
<entry>
<title>powerpc/64s: remove unneeded semicolon</title>
<updated>2021-04-22T15:38:04Z</updated>
<author>
<name>Yang Li</name>
<email>yang.lee@linux.alibaba.com</email>
</author>
<published>2021-02-02T03:34:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=caea7b833d866e0badf4b12dc41bf9fe6a7295f3'/>
<id>urn:sha1:caea7b833d866e0badf4b12dc41bf9fe6a7295f3</id>
<content type='text'>
Eliminate the following coccicheck warning:
./arch/powerpc/platforms/powernv/setup.c:160:2-3: Unneeded semicolon

Reported-by: Abaci Robot &lt;abaci@linux.alibaba.com&gt;
Signed-off-by: Yang Li &lt;yang.lee@linux.alibaba.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/1612236877-104974-1-git-send-email-yang.lee@linux.alibaba.com

</content>
</entry>
<entry>
<title>powerpc/pci: Move PHB discovery for PCI_DN using platforms</title>
<updated>2021-02-08T13:01:05Z</updated>
<author>
<name>Oliver O'Halloran</name>
<email>oohall@gmail.com</email>
</author>
<published>2020-11-03T04:35:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=fbbefb320214db14c3e740fce98e2c95c9d0669b'/>
<id>urn:sha1:fbbefb320214db14c3e740fce98e2c95c9d0669b</id>
<content type='text'>
Make powernv, pseries, powermac and maple use ppc_mc.discover_phbs.
These platforms need to be done together because they all depend on
pci_dn's being created from the DT. The pci_dn contains a pointer to
the relevant pci_controller so they need to be created after the
pci_controller structures are available, but before PCI devices are
scanned. Currently this ordering is provided by initcalls and the
sequence is:

  1. PHBs are discovered (setup_arch) (early boot, pre-initcalls)
  2. pci_dn are created from the unflattended DT (core initcall)
  3. PHBs are scanned pcibios_init() (subsys initcall)

The new ppc_md.discover_phbs() function is also a core_initcall so we
can't guarantee ordering between the creation of pci_controllers and
the creation of pci_dn's which require a pci_controller. We could use
the postcore, or core_sync initcall levels, but it's cleaner to just
move the pci_dn setup into the per-PHB inits which occur inside of
.discover_phb() for these platforms. This brings the boot-time path in
line with the PHB hotplug path that is used for pseries DLPAR
operations too.

Signed-off-by: Oliver O'Halloran &lt;oohall@gmail.com&gt;
[mpe: Squash powermac &amp; maple in to avoid breakage those platforms,
      convert memblock allocs to use kmalloc to avoid warnings]
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20201103043523.916109-2-oohall@gmail.com
</content>
</entry>
<entry>
<title>powerpc/64s/powernv: Fix memory corruption when saving SLB entries on MCE</title>
<updated>2020-12-02T12:16:40Z</updated>
<author>
<name>Nicholas Piggin</name>
<email>npiggin@gmail.com</email>
</author>
<published>2020-11-28T07:07:21Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=a1ee28117077c3bf24e5ab6324c835eaab629c45'/>
<id>urn:sha1:a1ee28117077c3bf24e5ab6324c835eaab629c45</id>
<content type='text'>
This can be hit by an HPT guest running on an HPT host and bring down
the host, so it's quite important to fix.

Fixes: 7290f3b3d3e6 ("powerpc/64s/powernv: machine check dump SLB contents")
Cc: stable@vger.kernel.org # v5.4+
Signed-off-by: Nicholas Piggin &lt;npiggin@gmail.com&gt;
Acked-by: Mahesh Salgaonkar &lt;mahesh@linux.ibm.com&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
Link: https://lore.kernel.org/r/20201128070728.825934-2-npiggin@gmail.com
</content>
</entry>
<entry>
<title>powerpc/64s: rename pnv|pseries_setup_rfi_flush to _setup_security_mitigations</title>
<updated>2020-11-19T12:47:25Z</updated>
<author>
<name>Daniel Axtens</name>
<email>dja@axtens.net</email>
</author>
<published>2020-11-17T05:59:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=da631f7fd623b6c180c8d93a93040d1e0d61291f'/>
<id>urn:sha1:da631f7fd623b6c180c8d93a93040d1e0d61291f</id>
<content type='text'>
pseries|pnv_setup_rfi_flush already does the count cache flush setup, and
we just added entry and uaccess flushes. So the name is not very accurate
any more. In both platforms we then also immediately setup the STF flush.

Rename them to _setup_security_mitigations and fold the STF flush in.

Signed-off-by: Daniel Axtens &lt;dja@axtens.net&gt;
Signed-off-by: Michael Ellerman &lt;mpe@ellerman.id.au&gt;
</content>
</entry>
</feed>
