linux-dev/arch/riscv/configs, branch master

riscv: enable CD-ROM file systems in defconfig

2022-08-26T00:01:09Z

CD-ROM images are still commonly used for installer images and other data exchange. These file systems should be supported on RISC-V by default like they are on x86_64. Signed-off-by: Heinrich Schuchardt Link: https://lore.kernel.org/r/20220812200853.311474-1-heinrich.schuchardt@canonical.com Signed-off-by: Palmer Dabbelt

riscv: enable Docker requirements in defconfig

2022-07-22T20:43:28Z

The defconfig kernel should be able to run Docker. Enable the missing settings according to [1]. make savedefconfig eliminates CONFIG_STACKTRACE which is enabled by default. Many of the settings are also needed to run a defconfig kernel on default distro installations or to run snaps. [1] https://github.com/moby/moby/blob/master/contrib/check-config.sh Signed-off-by: Heinrich Schuchardt Reviewed-by: Anup Patel Acked-by: Guo Ren Link: https://lore.kernel.org/r/20220608000251.55271-1-heinrich.schuchardt@canonical.com [Palmer: Drop BLK_CGROUP, as it's causing panics with KASAN] Signed-off-by: Palmer Dabbelt

RISC-V: Add CONFIG_{NON,}PORTABLE

2022-07-14T18:19:49Z

The RISC-V port has collected a handful of options that are fundamentally non-portable. To prevent users from shooting themselves in the foot, hide them all behind a config entry that explicitly calls out that non-portable binaries may be produced. Signed-off-by: Palmer Dabbelt Reviewed-by: Arnd Bergmann Signed-off-by: Palmer Dabbelt Reviewed-by: Atish Patra Reviewed-by: Damien Le Moal Reviewed-by: Guo Ren Link: https://lore.kernel.org/r/20220521193356.26562-1-palmer@rivosinc.com Signed-off-by: Palmer Dabbelt

riscv: config: enable SOC_STARFIVE in defconfig

2022-07-14T18:06:59Z

SOC_STARFIVE is the odd one out among the (compatible) SOC_FOO options as it is not enabled in the default defconfig. Add it to make catching dt regressions etc easier. Signed-off-by: Conor Dooley Acked-by: Emil Renner Berthing Link: https://lore.kernel.org/r/20220617182424.324276-1-mail@conchuod.ie Signed-off-by: Palmer Dabbelt

RISC-V: configs: Configs that had RPMSG_CHAR now get RPMSG_CTRL

2022-04-26T15:19:53Z

In the commit 617d32938d1b ("rpmsg: Move the rpmsg control device from rpmsg_char to rpmsg_ctrl"), we split the rpmsg_char driver in two. By default give everyone who had the old driver enabled the rpmsg_ctrl driver too. Signed-off-by: Arnaud Pouliquen Reviewed-by: Anup Patel Link: https://lore.kernel.org/r/20220404090527.582217-1-arnaud.pouliquen@foss.st.com Reviewed-by: Mathieu Poirier Signed-off-by: Palmer Dabbelt

RISC-V: K210 defconfigs: Drop redundant MEMBARRIER=n

2022-04-01T00:19:27Z

As of 93917ad50972 ("RISC-V: Add support for restartable sequence") we have support for restartable sequences, which default to enabled. These select MEMBARRIER, so disabling it is now redundant. Signed-off-by: Palmer Dabbelt

RISC-V: defconfig: Drop redundant SBI HVC and earlycon

2022-04-01T00:19:24Z

As of 3938d5a2f936 ("riscv: default to CONFIG_RISCV_SBI_V01=n") we no longer default to enabling SBI-0.1 support, so these dependent configs no longer have any effect. Remove them to avoid clutter. Signed-off-by: Palmer Dabbelt

RISC-V: Enable profiling by default

2022-03-31T20:28:32Z

Let us enable profiling by default in RV32 and RV64 defconfigs so that we can use RISC-V PMU drivers on various RISC-V platforms. Signed-off-by: Anup Patel Reviewed-by: Atish Patra Signed-off-by: Palmer Dabbelt

RISC-V CPU Idle Support

2022-03-30T23:17:54Z

This series adds RISC-V CPU Idle support using SBI HSM suspend function. The RISC-V SBI CPU idle driver added by this series is highly inspired from the ARM PSCI CPU idle driver. Special thanks Sandeep Tripathy for providing early feeback on SBI HSM support in all above projects (RISC-V SBI specification, OpenSBI, and Linux RISC-V). * palmer/riscv-idle: RISC-V: Enable RISC-V SBI CPU Idle driver for QEMU virt machine dt-bindings: Add common bindings for ARM and RISC-V idle states cpuidle: Add RISC-V SBI CPU idle driver cpuidle: Factor-out power domain related code from PSCI domain driver RISC-V: Add SBI HSM suspend related defines RISC-V: Add arch functions for non-retentive suspend entry/exit RISC-V: Rename relocate() and make it global RISC-V: Enable CPU_IDLE drivers

Merge tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2022-03-25T17:11:38Z

Pull RISC-V updates from Palmer Dabbelt: - Support for Sv57-based virtual memory. - Various improvements for the MicroChip PolarFire SOC and the associated Icicle dev board, which should allow upstream kernels to boot without any additional modifications. - An improved memmove() implementation. - Support for the new Ssconfpmf and SBI PMU extensions, which allows for a much more useful perf implementation on RISC-V systems. - Support for restartable sequences. * tag 'riscv-for-linus-5.18-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (36 commits) rseq/selftests: Add support for RISC-V RISC-V: Add support for restartable sequence MAINTAINERS: Add entry for RISC-V PMU drivers Documentation: riscv: Remove the old documentation RISC-V: Add sscofpmf extension support RISC-V: Add perf platform driver based on SBI PMU extension RISC-V: Add RISC-V SBI PMU extension definitions RISC-V: Add a simple platform driver for RISC-V legacy perf RISC-V: Add a perf core library for pmu drivers RISC-V: Add CSR encodings for all HPMCOUNTERS RISC-V: Remove the current perf implementation RISC-V: Improve /proc/cpuinfo output for ISA extensions RISC-V: Do no continue isa string parsing without correct XLEN RISC-V: Implement multi-letter ISA extension probing framework RISC-V: Extract multi-letter extension names from "riscv, isa" RISC-V: Minimal parser for "riscv, isa" strings RISC-V: Correctly print supported extensions riscv: Fixed misaligned memory access. Fixed pointer comparison. MAINTAINERS: update riscv/microchip entry riscv: dts: microchip: add new peripherals to icicle kit device tree ...