linux-dev/arch/riscv/include/asm/elf.h, branch linus/master

riscv: compat: vdso: Add setup additional pages implementation

2022-04-26T20:36:59Z

Reconstruct __setup_additional_pages() by appending vdso info pointer argument to meet compat_vdso_info requirement. And change vm_special_mapping *dm, *cm initialization into static. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Reviewed-by: Palmer Dabbelt Tested-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220405071314.3225832-18-guoren@kernel.org Signed-off-by: Palmer Dabbelt

riscv: compat: Add hw capability check for elf

2022-04-26T20:36:47Z

Detect hardware COMPAT (32bit U-mode) capability in rv64. If not support COMPAT mode in hw, compat_elf_check_arch would return false by compat_binfmt_elf.c Add CLASS to enhance (compat_)elf_check_arch to distinguish 32BIT/64BIT elf. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Tested-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220405071314.3225832-16-guoren@kernel.org Signed-off-by: Palmer Dabbelt

riscv: compat: Add elf.h implementation

2022-04-26T20:36:42Z

Implement necessary type and macro for compat elf. See the code comment for detail. Signed-off-by: Guo Ren Signed-off-by: Guo Ren Reviewed-by: Arnd Bergmann Tested-by: Heiko Stuebner Link: https://lore.kernel.org/r/20220405071314.3225832-15-guoren@kernel.org Signed-off-by: Palmer Dabbelt

riscv: Improve stack randomisation on RV64

2021-09-11T05:25:34Z

This enlarges the bits availiable for stack randomisation on RV64 from the default of 8MiB to 1GiB, to match arm64 and x86. Also, update the documentation to reflect our support for stack randomisation. Signed-off-by: Kefeng Wang [Palmer: commit text] Signed-off-by: Palmer Dabbelt

RISC-V: Add kdump support

2021-04-26T15:25:23Z

This patch adds support for kdump, the kernel will reserve a region for the crash kernel and jump there on panic. In order for userspace tools (kexec-tools) to prepare the crash kernel kexec image, we also need to expose some information on /proc/iomem for the memory regions used by the kernel and for the region reserved for crash kernel. Note that on userspace the device tree is used to determine the system's memory layout so the "System RAM" on /proc/iomem is ignored. I tested this on riscv64 qemu and works as expected, you may test it by triggering a crash through /proc/sysrq_trigger: echo c > /proc/sysrq_trigger Signed-off-by: Nick Kossifidis Signed-off-by: Palmer Dabbelt

riscv: Add cache information in AUX vector

2020-09-16T01:46:08Z

There are no standard CSR registers to provide cache information, the way for RISC-V is to get this information from DT. Currently, AT_L1I_X, AT_L1D_X and AT_L2_X are present in glibc header, and sysconf syscall could use them to get information of cache through AUX vector. The result of 'getconf -a' as follows: LEVEL1_ICACHE_SIZE 32768 LEVEL1_ICACHE_ASSOC 8 LEVEL1_ICACHE_LINESIZE 64 LEVEL1_DCACHE_SIZE 32768 LEVEL1_DCACHE_ASSOC 8 LEVEL1_DCACHE_LINESIZE 64 LEVEL2_CACHE_SIZE 2097152 LEVEL2_CACHE_ASSOC 32 LEVEL2_CACHE_LINESIZE 64 Signed-off-by: Zong Li Reviewed-by: Palmer Dabbelt Reviewed-by: Pekka Enberg Signed-off-by: Palmer Dabbelt

riscv: add nommu support

2019-11-17T23:17:39Z

The kernel runs in M-mode without using page tables, and thus can't run bare metal without help from additional firmware. Most of the patch is just stubbing out code not needed without page tables, but there is an interesting detail in the signals implementation: - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO entry point, but the ELF VDSO is not supported for nommu Linux. We instead copy the code to call the syscall onto the stack. In addition to enabling the nommu code a new defconfig for a small kernel image that can run in nommu mode on qemu is also provided, to run a kernel in qemu you can use the following command line: qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \ -kernel arch/riscv/boot/loader \ -drive file=rootfs.ext2,format=raw,id=hd0 \ -device virtio-blk-device,drive=hd0 Contains contributions from Damien Le Moal . Signed-off-by: Christoph Hellwig Reviewed-by: Anup Patel [paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards around PCI_IOBASE definition to fix build issues; fixed checkpatch issues; move the PCI_IO_* and VMEMMAP address space macros along with the others; resolve sparse warning] Signed-off-by: Paul Walmsley

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32Z

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman

riscv: remove unreachable big endian code

2019-04-25T21:51:10Z

RISC-V is always little endian. Signed-off-by: Christoph Hellwig Signed-off-by: Palmer Dabbelt

Move EM_RISCV into elf-em.h

2018-10-31T19:13:47Z

This should never have been inside our arch port to begin with, it's just a relic from when we were maintaining out of tree patches. Reviewed-by: Kees Cook Reviewed-by: Paul Walmsley Reviewed-by: Christoph Hellwig Tested-by: David Abdurachmanov Signed-off-by: Palmer Dabbelt