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<title>linux-dev/arch/riscv/kvm, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/riscv/kvm?h=master</id>
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<updated>2022-10-21T06:22:45Z</updated>
<entry>
<title>RISC-V: KVM: Fix kvm_riscv_vcpu_timer_pending() for Sstc</title>
<updated>2022-10-21T06:22:45Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-10-21T06:22:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=cea8896bd936135559253e9b23340cfa1cdf0caf'/>
<id>urn:sha1:cea8896bd936135559253e9b23340cfa1cdf0caf</id>
<content type='text'>
The kvm_riscv_vcpu_timer_pending() checks per-VCPU next_cycles
and per-VCPU software injected VS timer interrupt. This function
returns incorrect value when Sstc is available because the per-VCPU
next_cycles are only updated by kvm_riscv_vcpu_timer_save() called
from kvm_arch_vcpu_put(). As a result, when Sstc is available the
VCPU does not block properly upon WFI traps.

To fix the above issue, we introduce kvm_riscv_vcpu_timer_sync()
which will update per-VCPU next_cycles upon every VM exit instead
of kvm_riscv_vcpu_timer_save().

Fixes: 8f5cb44b1bae ("RISC-V: KVM: Support sstc extension")
Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'kvm-riscv-6.1-1' of https://github.com/kvm-riscv/linux into HEAD</title>
<updated>2022-10-03T19:33:43Z</updated>
<author>
<name>Paolo Bonzini</name>
<email>pbonzini@redhat.com</email>
</author>
<published>2022-10-03T19:33:43Z</published>
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<id>urn:sha1:e18d6152ff0f41b7f01f9817372022df04e0d354</id>
<content type='text'>
KVM/riscv changes for 6.1

- Improved instruction encoding infrastructure for
  instructions not yet supported by binutils
- Svinval support for both KVM Host and KVM Guest
- Zihintpause support for KVM Guest
- Zicbom support for KVM Guest
- Record number of signal exits as a VCPU stat
- Use generic guest entry infrastructure
</content>
</entry>
<entry>
<title>RISC-V: KVM: Use generic guest entry infrastructure</title>
<updated>2022-10-02T04:49:25Z</updated>
<author>
<name>Jisheng Zhang</name>
<email>jszhang@kernel.org</email>
</author>
<published>2022-10-02T04:49:25Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=9c00fbdd93a22a6657378292f2eb29e9754cde7f'/>
<id>urn:sha1:9c00fbdd93a22a6657378292f2eb29e9754cde7f</id>
<content type='text'>
Use generic guest entry infrastructure to properly handle
TIF_NOTIFY_RESUME.

Signed-off-by: Jisheng Zhang &lt;jszhang@kernel.org&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: KVM: Record number of signal exits as a vCPU stat</title>
<updated>2022-10-02T04:49:16Z</updated>
<author>
<name>Jisheng Zhang</name>
<email>jszhang@kernel.org</email>
</author>
<published>2022-10-02T04:49:16Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=54ce3f7ff3395f12ad142d46b628606ab1e926ef'/>
<id>urn:sha1:54ce3f7ff3395f12ad142d46b628606ab1e926ef</id>
<content type='text'>
Record a statistic indicating the number of times a vCPU has exited
due to a pending signal.

Signed-off-by: Jisheng Zhang &lt;jszhang@kernel.org&gt;
Reviewed-by: Guo Ren &lt;guoren@kernel.org&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org
</content>
</entry>
<entry>
<title>RISC-V: KVM: add __init annotation to riscv_kvm_init()</title>
<updated>2022-10-02T04:49:11Z</updated>
<author>
<name>Xiu Jianfeng</name>
<email>xiujianfeng@huawei.com</email>
</author>
<published>2022-10-02T04:49:11Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f493cdc92d9b9e9a0db0a9049609457e43a56066'/>
<id>urn:sha1:f493cdc92d9b9e9a0db0a9049609457e43a56066</id>
<content type='text'>
The riscv_kvm_init() is a module_init entry so let us add __init
annotation to it.

Signed-off-by: Xiu Jianfeng &lt;xiujianfeng@huawei.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: KVM: Expose Zicbom to the guest</title>
<updated>2022-10-02T04:49:05Z</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2022-10-02T04:49:05Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=56852c6211971798dfbe4098c8a8528b59234de2'/>
<id>urn:sha1:56852c6211971798dfbe4098c8a8528b59234de2</id>
<content type='text'>
Guests may use the cbo.inval,clean,flush instructions when the
CPU has the Zicbom extension and the hypervisor sets henvcfg.CBIE
(for cbo.inval) and henvcfg.CBCFE (for cbo.clean,flush).

Add Zicbom support for KVM guests which may be enabled and
disabled from KVM userspace using the ISA extension ONE_REG API.

Also opportunistically switch the other isa extension checks in
kvm_riscv_vcpu_update_config() to riscv_isa_extension_available().

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: KVM: Provide UAPI for Zicbom block size</title>
<updated>2022-10-02T04:48:59Z</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2022-10-02T04:48:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=afd5dde9a186b8fc5742fff707f184760c4af1a9'/>
<id>urn:sha1:afd5dde9a186b8fc5742fff707f184760c4af1a9</id>
<content type='text'>
We're about to allow guests to use the Zicbom extension. KVM
userspace needs to know the cache block size in order to
properly advertise it to the guest. Provide a virtual config
register for userspace to get it with the GET_ONE_REG API, but
setting it cannot be supported, so disallow SET_ONE_REG.

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Reviewed-by: Atish Patra &lt;atishp@rivosinc.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: KVM: Make ISA ext mappings explicit</title>
<updated>2022-10-02T04:48:54Z</updated>
<author>
<name>Andrew Jones</name>
<email>ajones@ventanamicro.com</email>
</author>
<published>2022-10-02T04:48:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=1b5cbb8733f924c99bc48a8e4c2a95449f0f514d'/>
<id>urn:sha1:1b5cbb8733f924c99bc48a8e4c2a95449f0f514d</id>
<content type='text'>
While adding new extensions at the bottom of the array isn't hard to
do, it's a pain to review in order to ensure we're not missing any.
Also, resolving merge conflicts for multiple new ISA extensions can be
error-prone. To make adding new mappings foolproof, explicitly assign
the array elements. And, now that the order doesn't matter, we can
alphabetize the extensions, so we do that too.

Signed-off-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: KVM: Allow Guest use Zihintpause extension</title>
<updated>2022-10-02T04:48:48Z</updated>
<author>
<name>Mayuresh Chitale</name>
<email>mchitale@ventanamicro.com</email>
</author>
<published>2022-10-02T04:48:48Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0bba48978f6b63aee0fa4ee3a8097ec94e75f7f2'/>
<id>urn:sha1:0bba48978f6b63aee0fa4ee3a8097ec94e75f7f2</id>
<content type='text'>
We should advertise Zihintpause ISA extension to KVM user-space whenever
host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
to pass on this information to Guest via ISA string.

Signed-off-by: Mayuresh Chitale &lt;mchitale@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: KVM: Allow Guest use Svinval extension</title>
<updated>2022-10-02T04:48:42Z</updated>
<author>
<name>Anup Patel</name>
<email>apatel@ventanamicro.com</email>
</author>
<published>2022-10-02T04:48:42Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=bad6ea07c876a67c4d8f46b0c565ab500150720f'/>
<id>urn:sha1:bad6ea07c876a67c4d8f46b0c565ab500150720f</id>
<content type='text'>
We should advertise Svinval ISA extension to KVM user-space whenever
host supports it. This will allow KVM user-space (i.e. QEMU or KVMTOOL)
to pass on this information to Guest via ISA string.

Signed-off-by: Anup Patel &lt;apatel@ventanamicro.com&gt;
Reviewed-by: Andrew Jones &lt;ajones@ventanamicro.com&gt;
Signed-off-by: Anup Patel &lt;anup@brainfault.org&gt;
</content>
</entry>
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