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<title>linux-dev/arch/riscv/lib/Makefile, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/riscv/lib/Makefile?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/riscv/lib/Makefile?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2021-01-14T23:09:09Z</updated>
<entry>
<title>riscv: Add support for function error injection</title>
<updated>2021-01-14T23:09:09Z</updated>
<author>
<name>Guo Ren</name>
<email>guoren@linux.alibaba.com</email>
</author>
<published>2020-12-17T16:01:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ee55ff803b383e03d0855661d3416aa1763e54f9'/>
<id>urn:sha1:ee55ff803b383e03d0855661d3416aa1763e54f9</id>
<content type='text'>
Inspired by the commit 42d038c4fb00 ("arm64: Add support for function
error injection"), this patch supports function error injection for
riscv.

This patch mainly support two functions: one is regs_set_return_value()
which is used to overwrite the return value; the another function is
override_function_with_return() which is to override the probed
function returning and jump to its caller.

Test log:
 cd /sys/kernel/debug/fail_function
 echo sys_clone &gt; inject
 echo 100 &gt; probability
 echo 1 &gt; interval
 ls /
[  313.176875] FAULT_INJECTION: forcing a failure.
[  313.176875] name fail_function, interval 1, probability 100, space 0, times 1
[  313.184357] CPU: 0 PID: 87 Comm: sh Not tainted 5.8.0-rc5-00007-g6a758cc #117
[  313.187616] Call Trace:
[  313.189100] [&lt;ffffffe0002036b6&gt;] walk_stackframe+0x0/0xc2
[  313.191626] [&lt;ffffffe00020395c&gt;] show_stack+0x40/0x4c
[  313.193927] [&lt;ffffffe000556c60&gt;] dump_stack+0x7c/0x96
[  313.194795] [&lt;ffffffe0005522e8&gt;] should_fail+0x140/0x142
[  313.195923] [&lt;ffffffe000299ffc&gt;] fei_kprobe_handler+0x2c/0x5a
[  313.197687] [&lt;ffffffe0009e2ec4&gt;] kprobe_breakpoint_handler+0xb4/0x18a
[  313.200054] [&lt;ffffffe00020357e&gt;] do_trap_break+0x36/0xca
[  313.202147] [&lt;ffffffe000201bca&gt;] ret_from_exception+0x0/0xc
[  313.204556] [&lt;ffffffe000201bbc&gt;] ret_from_syscall+0x0/0x2
-sh: can't fork: Invalid argument

Signed-off-by: Guo Ren &lt;guoren@linux.alibaba.com&gt;
Reviewed-by: Masami Hiramatsu &lt;mhiramat@kernel.org&gt;
Cc: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
Cc: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: provide memmove implementation</title>
<updated>2020-12-11T01:27:54Z</updated>
<author>
<name>Nylon Chen</name>
<email>nylon7@andestech.com</email>
</author>
<published>2020-11-30T09:13:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=04091d6c0535f6dc82af864ab56425235c6581a4'/>
<id>urn:sha1:04091d6c0535f6dc82af864ab56425235c6581a4</id>
<content type='text'>
The memmove used by the kernel feature like KASAN.

Signed-off-by: Nick Hu &lt;nickhu@andestech.com&gt;
Signed-off-by: Nick Hu &lt;nick650823@gmail.com&gt;
Signed-off-by: Nylon Chen &lt;nylon7@andestech.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: use memcpy based uaccess for nommu again</title>
<updated>2020-10-04T17:27:07Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2020-09-07T05:58:22Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=11129e8ed4d91a062c5062d80f476adc7fbedbac'/>
<id>urn:sha1:11129e8ed4d91a062c5062d80f476adc7fbedbac</id>
<content type='text'>
This reverts commit adccfb1a805ea84d2db38eb53032533279bdaa97.

Now that the generic uaccess by mempcy code handles unaligned addresses
the generic code can be used for all RISC-V CPUs.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: uaccess should be used in nommu mode</title>
<updated>2020-03-19T01:44:30Z</updated>
<author>
<name>Greentime Hu</name>
<email>greentime.hu@sifive.com</email>
</author>
<published>2020-03-03T09:34:17Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=adccfb1a805ea84d2db38eb53032533279bdaa97'/>
<id>urn:sha1:adccfb1a805ea84d2db38eb53032533279bdaa97</id>
<content type='text'>
It might have the unaligned access exception when trying to exchange data
with user space program. In this case, it failed in tty_ioctl(). Therefore
we should enable uaccess.S for NOMMU mode since the generic code doesn't
handle the unaligned access cases.

   0x8013a212 &lt;tty_ioctl+462&gt;:  ld      a5,460(s1)

[    0.115279] Oops - load address misaligned [#1]
[    0.115284] CPU: 0 PID: 29 Comm: sh Not tainted 5.4.0-rc5-00020-gb4c27160d562-dirty #36
[    0.115294] epc: 000000008013a212 ra : 000000008013a212 sp : 000000008f48dd50
[    0.115303]  gp : 00000000801cac28 tp : 000000008fb80000 t0 : 00000000000000e8
[    0.115312]  t1 : 000000008f58f108 t2 : 0000000000000009 s0 : 000000008f48ddf0
[    0.115321]  s1 : 000000008f8c6220 a0 : 0000000000000001 a1 : 000000008f48dd28
[    0.115330]  a2 : 000000008fb80000 a3 : 00000000801a7398 a4 : 0000000000000000
[    0.115339]  a5 : 0000000000000000 a6 : 000000008f58f0c6 a7 : 000000000000001d
[    0.115348]  s2 : 000000008f8c6308 s3 : 000000008f78b7c8 s4 : 000000008fb834c0
[    0.115357]  s5 : 0000000000005413 s6 : 0000000000000000 s7 : 000000008f58f2b0
[    0.115366]  s8 : 000000008f858008 s9 : 000000008f776818 s10: 000000008f776830
[    0.115375]  s11: 000000008fb840a8 t3 : 1999999999999999 t4 : 000000008f78704c
[    0.115384]  t5 : 0000000000000005 t6 : 0000000000000002
[    0.115391] status: 0000000200001880 badaddr: 000000008f8c63ec cause: 0000000000000004
[    0.115401] ---[ end trace 00d490c6a8b6c9ac ]---

This failure could be fixed after this patch applied.

[    0.002282] Run /init as init process
Initializing random number generator... [    0.005573] random: dd: uninitialized urandom read (512 bytes read)
done.

Welcome to Buildroot
buildroot login: root
Password:
Jan  1 00:00:00 login[62]: root login on 'ttySIF0'
~ #

Signed-off-by: Greentime Hu &lt;greentime.hu@sifive.com&gt;
Reviewed-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmerdabbelt@google.com&gt;
</content>
</entry>
<entry>
<title>riscv: add nommu support</title>
<updated>2019-11-17T23:17:39Z</updated>
<author>
<name>Christoph Hellwig</name>
<email>hch@lst.de</email>
</author>
<published>2019-10-28T12:10:41Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=6bd33e1ece528f67646db33bf97406b747dafda0'/>
<id>urn:sha1:6bd33e1ece528f67646db33bf97406b747dafda0</id>
<content type='text'>
The kernel runs in M-mode without using page tables, and thus can't run
bare metal without help from additional firmware.

Most of the patch is just stubbing out code not needed without page
tables, but there is an interesting detail in the signals implementation:

 - The normal RISC-V syscall ABI only implements rt_sigreturn as VDSO
   entry point, but the ELF VDSO is not supported for nommu Linux.
   We instead copy the code to call the syscall onto the stack.

In addition to enabling the nommu code a new defconfig for a small
kernel image that can run in nommu mode on qemu is also provided, to run
a kernel in qemu you can use the following command line:

qemu-system-riscv64 -smp 2 -m 64 -machine virt -nographic \
	-kernel arch/riscv/boot/loader \
	-drive file=rootfs.ext2,format=raw,id=hd0 \
	-device virtio-blk-device,drive=hd0

Contains contributions from Damien Le Moal &lt;Damien.LeMoal@wdc.com&gt;.

Signed-off-by: Christoph Hellwig &lt;hch@lst.de&gt;
Reviewed-by: Anup Patel &lt;anup@brainfault.org&gt;
[paul.walmsley@sifive.com: updated to apply; add CONFIG_MMU guards
 around PCI_IOBASE definition to fix build issues; fixed checkpatch
 issues; move the PCI_IO_* and VMEMMAP address space macros along
 with the others; resolve sparse warning]
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>RISC-V: Remove udivdi3</title>
<updated>2019-08-08T23:05:38Z</updated>
<author>
<name>Palmer Dabbelt</name>
<email>palmer@sifive.com</email>
</author>
<published>2019-08-07T00:05:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=81a48ee417387bef9cb720ca75980ee11ae9c901'/>
<id>urn:sha1:81a48ee417387bef9cb720ca75980ee11ae9c901</id>
<content type='text'>
This should never have landed in the first place: it was added as part
of 64-bit divide support for 32-bit systems, but the kernel doesn't
allow this sort of division.  I must have forgotten to remove it.

This patch removes the support.  Since this routine only worked on
64-bit platforms but was only built on 32-bit platforms, it's
essentially just nonsense anyway.

Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
Acked-by: Nicolas Pitre &lt;nico@fluxnic.net&gt;
Link: https://lore.kernel.org/linux-riscv/nycvar.YSQ.7.76.1908061413360.19480@knanqh.ubzr/T/#t
Reported-by: Eric Lin &lt;tesheng@andestech.com&gt;
Signed-off-by: Paul Walmsley &lt;paul.walmsley@sifive.com&gt;</content>
</entry>
<entry>
<title>treewide: Add SPDX license identifier - Makefile/Kconfig</title>
<updated>2019-05-21T08:50:46Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-19T12:07:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1'/>
<id>urn:sha1:ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1</id>
<content type='text'>
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>RISC-V: lib: Fix build error for 64-bit</title>
<updated>2018-11-13T02:09:55Z</updated>
<author>
<name>Olof Johansson</name>
<email>olof@lixom.net</email>
</author>
<published>2018-10-31T06:47:07Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=85d90b91807bb0c4a0fcff6a144e73f11cda782a'/>
<id>urn:sha1:85d90b91807bb0c4a0fcff6a144e73f11cda782a</id>
<content type='text'>
Fixes the following build error from tinyconfig:

riscv64-unknown-linux-gnu-ld: kernel/sched/fair.o: in function `.L8':
fair.c:(.text+0x70): undefined reference to `__lshrti3'
riscv64-unknown-linux-gnu-ld: kernel/time/clocksource.o: in function `.L0 ':
clocksource.c:(.text+0x334): undefined reference to `__lshrti3'

Fixes: 7f47c73b355f ("RISC-V: Build tishift only on 64-bit")
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: Build tishift only on 64-bit</title>
<updated>2018-10-23T00:02:55Z</updated>
<author>
<name>Zong Li</name>
<email>zongbox@gmail.com</email>
</author>
<published>2018-10-02T08:52:27Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7f47c73b355f300cf162f3a664e43d557d2cb30d'/>
<id>urn:sha1:7f47c73b355f300cf162f3a664e43d557d2cb30d</id>
<content type='text'>
Only RV64 supports 128 integer size.

Signed-off-by: Zong Li &lt;zong@andestech.com&gt;
Reviewed-by: Christoph Hellwig &lt;hch@lst.de&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
<entry>
<title>RISC-V: implement __lshrti3.</title>
<updated>2018-08-13T15:31:30Z</updated>
<author>
<name>Alex Guo</name>
<email>xfguo@jlsemi.com</email>
</author>
<published>2018-07-29T01:14:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=a89757daf25cfe5320a5f40773271d86e2456c10'/>
<id>urn:sha1:a89757daf25cfe5320a5f40773271d86e2456c10</id>
<content type='text'>
Signed-off-by: Alex Guo &lt;xfguo@jlsemi.com&gt;
Signed-off-by: Palmer Dabbelt &lt;palmer@sifive.com&gt;
</content>
</entry>
</feed>
