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<title>linux-dev/arch/sh/include/asm/cachectl.h, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/sh/include/asm/cachectl.h?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/sh/include/asm/cachectl.h?h=master'/>
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<updated>2012-10-09T08:47:37Z</updated>
<entry>
<title>UAPI: (Scripted) Disintegrate arch/sh/include/asm</title>
<updated>2012-10-09T08:47:37Z</updated>
<author>
<name>David Howells</name>
<email>dhowells@redhat.com</email>
</author>
<published>2012-10-09T08:47:37Z</published>
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<id>urn:sha1:0a9426df1858f71ac84eb7eef500b4247de5e3bb</id>
<content type='text'>
Signed-off-by: David Howells &lt;dhowells@redhat.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Acked-by: Michael Kerrisk &lt;mtk.manpages@gmail.com&gt;
Acked-by: Paul E. McKenney &lt;paulmck@linux.vnet.ibm.com&gt;
Acked-by: Dave Jones &lt;davej@redhat.com&gt;
</content>
</entry>
<entry>
<title>sh: fix sys_cacheflush error checking</title>
<updated>2009-08-24T09:59:09Z</updated>
<author>
<name>Giuseppe Cavallaro</name>
<email>peppe.cavallaro@st.com</email>
</author>
<published>2009-08-24T09:59:09Z</published>
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<id>urn:sha1:788e6af37a4ace8721eda72e4abe66fe0f6b49fd</id>
<content type='text'>
sys_cacheflush should return with EINVAL if the cache parameter is not
one of ICACHE, DCACHE or BCACHE.
So, we need to include 0 in the first check.

It also adds the three definitions above as wrapper of the existent macros.

PS: ltp cacheflush01 test now passes.

Signed-off-by: Giuseppe Cavallaro &lt;peppe.cavallaro@st.com&gt;
Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
<entry>
<title>sh: Add sys_cacheflush() call for SH CPUs.</title>
<updated>2009-08-24T09:16:56Z</updated>
<author>
<name>Stuart Menefy</name>
<email>stuart.menefy@st.com</email>
</author>
<published>2009-08-24T09:16:56Z</published>
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<id>urn:sha1:6d243dd37002bcee54841852ab1b8606fd457851</id>
<content type='text'>
Adds a system call to allow user code to flush code from the cache.
You can use instructions for the data side, but the iside can
only be done by a flush ROM which really only works with a direct
mapped cache. The later SH4's have 2 way Iside, so this call allows
a portable way to flush the cache.

Signed-off-by: Stuart Menefy &lt;stuart.menefy@st.com&gt;
Signed-off-by: Paul Mundt &lt;lethal@linux-sh.org&gt;
</content>
</entry>
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