<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/sparc64/kernel/winfixup.S, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/sparc64/kernel/winfixup.S?h=master</id>
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<updated>2008-12-04T17:17:21Z</updated>
<entry>
<title>sparc,sparc64: unify kernel/</title>
<updated>2008-12-04T17:17:21Z</updated>
<author>
<name>Sam Ravnborg</name>
<email>sam@ravnborg.org</email>
</author>
<published>2008-12-03T11:11:52Z</published>
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<id>urn:sha1:a88b5ba8bd8ac18aad65ee6c6a254e2e74876db3</id>
<content type='text'>
o Move all files from sparc64/kernel/ to sparc/kernel
  - rename as appropriate
o Update sparc/Makefile to the changes
o Update sparc/kernel/Makefile to include the sparc64 files

NOTE: This commit changes link order on sparc64!

Link order had to change for either of sparc32 and sparc64.
And assuming sparc64 see more testing than sparc32 change link
order on sparc64 where issues will be caught faster.

Signed-off-by: Sam Ravnborg &lt;sam@ravnborg.org&gt;
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: %l6 trap return handling no longer necessary.</title>
<updated>2008-04-24T10:15:22Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2008-04-24T10:15:22Z</published>
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<id>urn:sha1:7697daaa894ca2bc5cd652269c316bcdc3ec441b</id>
<content type='text'>
Now that we indicate the "restart system call" in the
trap type field of pt_regs-&gt;magic, we don't need to
set the %l6 boolean in all of the trap return paths.

And we therefore don't need to pass it to do_notify_resume().

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Fix unaligned access winfxup handling on SUN4V.</title>
<updated>2006-03-20T09:13:39Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@sunset.davemloft.net</email>
</author>
<published>2006-02-19T00:39:39Z</published>
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<id>urn:sha1:24c523ecc667dfeb28ef969cfabc531709bfffb8</id>
<content type='text'>
Another case where we have to force ourselves into global register
level one.  Also make sure the arguments passed to sun4v_do_mna() are
correct.

This area actually needs some more work, for example spill fixup is
not necessarily going to do the right thing for this case.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Fix bogus call to sun4v_mna in winfixup code.</title>
<updated>2006-03-20T09:13:13Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@sunset.davemloft.net</email>
</author>
<published>2006-02-16T09:45:49Z</published>
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<id>urn:sha1:9b6b46470cc1c52f6917b0cd8b7cf4b5cbc5acf6</id>
<content type='text'>
The C function is named sun4v_do_mna not sun4v_mna.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: SUN4V memory exception trap handlers.</title>
<updated>2006-03-20T09:12:07Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@sunset.davemloft.net</email>
</author>
<published>2006-02-10T04:20:34Z</published>
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<id>urn:sha1:ed6b0b45437dcf7ef1c48b3be413bebcc84771d8</id>
<content type='text'>
Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Refine register window trap handling.</title>
<updated>2006-03-20T09:11:36Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@sunset.davemloft.net</email>
</author>
<published>2006-02-04T08:10:01Z</published>
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<id>urn:sha1:314ef6859750b6539eac48d78059bb7986f29cb1</id>
<content type='text'>
When saving and restoing trap state, do the window spill/fill
handling inline so that we never trap deeper than 2 trap levels.
This is important for chips like Niagara.

The window fixup code is massively simplified, and many more
improvements are now possible.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Add explicit register args to trap state loading macros.</title>
<updated>2006-03-20T09:11:35Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@sunset.davemloft.net</email>
</author>
<published>2006-02-03T05:55:10Z</published>
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<id>urn:sha1:ffe483d55229fadbaf4cc7316d47024a24ecd1a2</id>
<content type='text'>
This, as well as making the code cleaner, allows a simplification in
the TSB miss handling path.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Don't clobber alt-global %g4 on window fixups.</title>
<updated>2006-03-20T09:11:30Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2006-02-01T02:35:05Z</published>
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<id>urn:sha1:30a6ecad9670d97c9d0fbfa7d80970aeb339bdec</id>
<content type='text'>
If we are returning back to kernel mode, %g4 could be live
(for example, in the case where we window spill in the etrap
code).  So do not change it's value if going back to kernel.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Fix race in LOAD_PER_CPU_BASE()</title>
<updated>2006-03-20T09:11:29Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2006-02-01T02:34:51Z</published>
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<id>urn:sha1:86b818687d4894063ecd1190e54717a0cce8c009</id>
<content type='text'>
Since we use %g5 itself as a temporary, it can get clobbered
if we take an interrupt mid-stream and thus cause end up with
the final %g5 value too early as a result of rtrap processing.

Set %g5 at the very end, atomically, to avoid this problem.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
<entry>
<title>[SPARC64]: Fix bogus flush instruction usage.</title>
<updated>2006-03-20T09:11:22Z</updated>
<author>
<name>David S. Miller</name>
<email>davem@davemloft.net</email>
</author>
<published>2006-02-01T02:33:00Z</published>
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<id>urn:sha1:4da808c352c290d3f762933d44d4ab90c2fd65f3</id>
<content type='text'>
Some of the trap code was still assuming that alternate
global %g6 was hard coded with current_thread_info().
Let's just consistently flush at KERNBASE when we need
a pipeline synchronization.  That's locked into the TLB
and will always work.

Signed-off-by: David S. Miller &lt;davem@davemloft.net&gt;
</content>
</entry>
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