<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/x86/events/intel, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/x86/events/intel?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/arch/x86/events/intel?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-11-02T11:22:07Z</updated>
<entry>
<title>perf/x86/intel: Add Cooper Lake stepping to isolation_ucodes[]</title>
<updated>2022-11-02T11:22:07Z</updated>
<author>
<name>Kan Liang</name>
<email>kan.liang@linux.intel.com</email>
</author>
<published>2022-10-31T15:45:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=6f8faf471446844bb9c318e0340221049d5c19f4'/>
<id>urn:sha1:6f8faf471446844bb9c318e0340221049d5c19f4</id>
<content type='text'>
The intel_pebs_isolation quirk checks both model number and stepping.
Cooper Lake has a different stepping (11) than the other Skylake Xeon.
It cannot benefit from the optimization in commit 9b545c04abd4f
("perf/x86/kvm: Avoid unnecessary work in guest filtering").

Add the stepping of Cooper Lake into the isolation_ucodes[] table.

Signed-off-by: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20221031154550.571663-1-kan.liang@linux.intel.com
</content>
</entry>
<entry>
<title>perf/x86/intel: Fix pebs event constraints for SPR</title>
<updated>2022-11-02T11:22:06Z</updated>
<author>
<name>Kan Liang</name>
<email>kan.liang@linux.intel.com</email>
</author>
<published>2022-10-31T15:41:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0916886bb978e7eae1ca3955ba07f51c020da20c'/>
<id>urn:sha1:0916886bb978e7eae1ca3955ba07f51c020da20c</id>
<content type='text'>
According to the latest event list, update the MEM_INST_RETIRED events
which support the DataLA facility for SPR.

Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20221031154119.571386-2-kan.liang@linux.intel.com
</content>
</entry>
<entry>
<title>perf/x86/intel: Fix pebs event constraints for ICL</title>
<updated>2022-11-02T11:22:06Z</updated>
<author>
<name>Kan Liang</name>
<email>kan.liang@linux.intel.com</email>
</author>
<published>2022-10-31T15:41:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=acc5568b90c19ac6375508a93b9676cd18a92a35'/>
<id>urn:sha1:acc5568b90c19ac6375508a93b9676cd18a92a35</id>
<content type='text'>
According to the latest event list, update the MEM_INST_RETIRED events
which support the DataLA facility.

Fixes: 6017608936c1 ("perf/x86/intel: Add Icelake support")
Reported-by: Jannis Klinkenberg &lt;jannis.klinkenberg@rwth-aachen.de&gt;
Signed-off-by: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Cc: stable@vger.kernel.org
Link: https://lkml.kernel.org/r/20221031154119.571386-1-kan.liang@linux.intel.com
</content>
</entry>
<entry>
<title>perf/x86/intel/lbr: Use setup_clear_cpu_cap() instead of clear_cpu_cap()</title>
<updated>2022-10-20T15:10:28Z</updated>
<author>
<name>Maxim Levitsky</name>
<email>mlevitsk@redhat.com</email>
</author>
<published>2022-07-18T14:11:19Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b329f5ddc9ce4b622d9c7aaf5c6df4de52caf91a'/>
<id>urn:sha1:b329f5ddc9ce4b622d9c7aaf5c6df4de52caf91a</id>
<content type='text'>
clear_cpu_cap(&amp;boot_cpu_data) is very similar to setup_clear_cpu_cap()
except that the latter also sets a bit in 'cpu_caps_cleared' which
later clears the same cap in secondary cpus, which is likely what is
meant here.

Fixes: 47125db27e47 ("perf/x86/intel/lbr: Support Architectural LBR")
Signed-off-by: Maxim Levitsky &lt;mlevitsk@redhat.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Reviewed-by: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Link: https://lkml.kernel.org/r/20220718141123.136106-2-mlevitsk@redhat.com
</content>
</entry>
<entry>
<title>Merge tag 'perf-core-2022-10-07' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2022-10-10T16:27:46Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-10-10T16:27:46Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3871d93b82a4a6c1f4308064f046a544f16ada21'/>
<id>urn:sha1:3871d93b82a4a6c1f4308064f046a544f16ada21</id>
<content type='text'>
Pull perf events updates from Ingo Molnar:
 "PMU driver updates:

   - Add AMD Last Branch Record Extension Version 2 (LbrExtV2) feature
     support for Zen 4 processors.

   - Extend the perf ABI to provide branch speculation information, if
     available, and use this on CPUs that have it (eg. LbrExtV2).

   - Improve Intel PEBS TSC timestamp handling &amp; integration.

   - Add Intel Raptor Lake S CPU support.

   - Add 'perf mem' and 'perf c2c' memory profiling support on AMD CPUs
     by utilizing IBS tagged load/store samples.

   - Clean up &amp; optimize various x86 PMU details.

  HW breakpoints:

   - Big rework to optimize the code for systems with hundreds of CPUs
     and thousands of breakpoints:

      - Replace the nr_bp_mutex global mutex with the bp_cpuinfo_sem
        per-CPU rwsem that is read-locked during most of the key
        operations.

      - Improve the O(#cpus * #tasks) logic in toggle_bp_slot() and
        fetch_bp_busy_slots().

      - Apply micro-optimizations &amp; cleanups.

  - Misc cleanups &amp; enhancements"

* tag 'perf-core-2022-10-07' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (75 commits)
  perf/hw_breakpoint: Annotate tsk-&gt;perf_event_mutex vs ctx-&gt;mutex
  perf: Fix pmu_filter_match()
  perf: Fix lockdep_assert_event_ctx()
  perf/x86/amd/lbr: Adjust LBR regardless of filtering
  perf/x86/utils: Fix uninitialized var in get_branch_type()
  perf/uapi: Define PERF_MEM_SNOOPX_PEER in kernel header file
  perf/x86/amd: Support PERF_SAMPLE_PHY_ADDR
  perf/x86/amd: Support PERF_SAMPLE_ADDR
  perf/x86/amd: Support PERF_SAMPLE_{WEIGHT|WEIGHT_STRUCT}
  perf/x86/amd: Support PERF_SAMPLE_DATA_SRC
  perf/x86/amd: Add IBS OP_DATA2 DataSrc bit definitions
  perf/mem: Introduce PERF_MEM_LVLNUM_{EXTN_MEM|IO}
  perf/x86/uncore: Add new Raptor Lake S support
  perf/x86/cstate: Add new Raptor Lake S support
  perf/x86/msr: Add new Raptor Lake S support
  perf/x86: Add new Raptor Lake S support
  bpf: Check flags for branch stack in bpf_read_branch_records helper
  perf, hw_breakpoint: Fix use-after-free if perf_event_open() fails
  perf: Use sample_flags for raw_data
  perf: Use sample_flags for addr
  ...
</content>
</entry>
<entry>
<title>perf/x86/uncore: Add new Raptor Lake S support</title>
<updated>2022-09-29T10:20:53Z</updated>
<author>
<name>Kan Liang</name>
<email>kan.liang@linux.intel.com</email>
</author>
<published>2022-09-28T15:33:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=e04a1607c9c3c0e2dc48715aeb570f2581f514bc'/>
<id>urn:sha1:e04a1607c9c3c0e2dc48715aeb570f2581f514bc</id>
<content type='text'>
From the perspective of the uncore PMU, the new Raptor Lake S is the
same as the other hybrid {ALDER,RAPTOP}LAKE.

Signed-off-by: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lore.kernel.org/r/20220928153331.3757388-4-kan.liang@linux.intel.com
</content>
</entry>
<entry>
<title>perf/x86/cstate: Add new Raptor Lake S support</title>
<updated>2022-09-29T10:20:53Z</updated>
<author>
<name>Kan Liang</name>
<email>kan.liang@linux.intel.com</email>
</author>
<published>2022-09-28T15:33:30Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d12940d2ead51c6978e7d38b2abf12b833270b2a'/>
<id>urn:sha1:d12940d2ead51c6978e7d38b2abf12b833270b2a</id>
<content type='text'>
From the perspective of Intel cstate residency counters, the new
Raptor Lake S is the same as the other hybrid {ALDER,RAPTOP}LAKE.

Signed-off-by: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lore.kernel.org/r/20220928153331.3757388-3-kan.liang@linux.intel.com
</content>
</entry>
<entry>
<title>perf/x86: Add new Raptor Lake S support</title>
<updated>2022-09-29T10:20:52Z</updated>
<author>
<name>Kan Liang</name>
<email>kan.liang@linux.intel.com</email>
</author>
<published>2022-09-28T15:33:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=50b0c97bf00e4815aee09cace28b940ebb060e69'/>
<id>urn:sha1:50b0c97bf00e4815aee09cace28b940ebb060e69</id>
<content type='text'>
From PMU's perspective, the new Raptor Lake S is the same as the other
of hybrid {ALDER,RAPTOP}LAKE.

Signed-off-by: Kan Liang &lt;kan.liang@linux.intel.com&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lore.kernel.org/r/20220928153331.3757388-1-kan.liang@linux.intel.com
</content>
</entry>
<entry>
<title>Merge branch 'v6.0-rc7'</title>
<updated>2022-09-29T10:20:50Z</updated>
<author>
<name>Peter Zijlstra</name>
<email>peterz@infradead.org</email>
</author>
<published>2022-09-29T10:20:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=a1ebcd59430236b336428bbf8e1da16fb87d56e4'/>
<id>urn:sha1:a1ebcd59430236b336428bbf8e1da16fb87d56e4</id>
<content type='text'>
Merge upstream to get RAPTORLAKE_S

Signed-off-by: Peter Zijlstra &lt;peterz@infradead.org&gt;
</content>
</entry>
<entry>
<title>perf: Use sample_flags for addr</title>
<updated>2022-09-27T20:50:24Z</updated>
<author>
<name>Namhyung Kim</name>
<email>namhyung@kernel.org</email>
</author>
<published>2022-09-21T22:00:31Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7b084630153152239d84990ac4540c2dd360186f'/>
<id>urn:sha1:7b084630153152239d84990ac4540c2dd360186f</id>
<content type='text'>
Use the new sample_flags to indicate whether the addr field is filled by
the PMU driver.  As most PMU drivers pass 0, it can set the flag only if
it has a non-zero value.  And use 0 in perf_sample_output() if it's not
filled already.

Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
Signed-off-by: Peter Zijlstra (Intel) &lt;peterz@infradead.org&gt;
Link: https://lkml.kernel.org/r/20220921220032.2858517-1-namhyung@kernel.org
</content>
</entry>
</feed>
