<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/arch/x86/kernel/cpu/mce/severity.c, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/arch/x86/kernel/cpu/mce/severity.c?h=linus%2Fmaster</id>
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<updated>2022-04-25T10:40:48Z</updated>
<entry>
<title>x86/mce: Add messages for panic errors in AMD's MCE grading</title>
<updated>2022-04-25T10:40:48Z</updated>
<author>
<name>Carlos Bilbao</name>
<email>carlos.bilbao@amd.com</email>
</author>
<published>2022-04-05T18:32:14Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=fa619f5156cf1ee3773edc6d756be262c9ef35de'/>
<id>urn:sha1:fa619f5156cf1ee3773edc6d756be262c9ef35de</id>
<content type='text'>
When a machine error is graded as PANIC by the AMD grading logic, the
MCE handler calls mce_panic(). The notification chain does not come
into effect so the AMD EDAC driver does not decode the errors. In these
cases, the messages displayed to the user are more cryptic and miss
information that might be relevant, like the context in which the error
took place.

Add messages to the grading logic for machine errors so that it is clear
what error it was.

  [ bp: Massage commit message. ]

Signed-off-by: Carlos Bilbao &lt;carlos.bilbao@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Yazen Ghannam &lt;yazen.ghannam@amd.com&gt;
Link: https://lore.kernel.org/r/20220405183212.354606-3-carlos.bilbao@amd.com
</content>
</entry>
<entry>
<title>x86/mce: Simplify AMD severity grading logic</title>
<updated>2022-04-25T10:32:03Z</updated>
<author>
<name>Carlos Bilbao</name>
<email>carlos.bilbao@amd.com</email>
</author>
<published>2022-04-05T18:32:13Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=70c459d915e838b7f536b8e26e0b3a6141bd2645'/>
<id>urn:sha1:70c459d915e838b7f536b8e26e0b3a6141bd2645</id>
<content type='text'>
The MCE handler needs to understand the severity of the machine errors to
act accordingly. Simplify the AMD grading logic following a logic that
closely resembles the descriptions of the public PPR documents. This will
help include more fine-grained grading of errors in the future.

  [ bp: Touchups. ]

Signed-off-by: Carlos Bilbao &lt;carlos.bilbao@amd.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Yazen Ghannam &lt;yazen.ghannam@amd.com&gt;
Link: https://lore.kernel.org/r/20220405183212.354606-2-carlos.bilbao@amd.com
</content>
</entry>
<entry>
<title>x86/mce: Remove the tolerance level control</title>
<updated>2022-02-23T10:09:25Z</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2021-12-20T20:43:28Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7f1b8e0d6360178e3527d4f14e6921c254a86035'/>
<id>urn:sha1:7f1b8e0d6360178e3527d4f14e6921c254a86035</id>
<content type='text'>
This is pretty much unused and not really useful. What is more, all
relevant MCA hardware has recoverable machine checks support so there's
no real need to tweak MCA tolerance levels in order to *maybe* extend
machine lifetime.

So rip it out.

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lore.kernel.org/r/YcDq8PxvKtTENl/e@zn.tnic
</content>
</entry>
<entry>
<title>x86/mce: Use arch atomic and bit helpers</title>
<updated>2022-02-13T21:08:27Z</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2022-02-04T08:30:15Z</published>
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<id>urn:sha1:f11445ba7a1160b87615e3f863a9e66c85189399</id>
<content type='text'>
The arch helpers do not have explicit KASAN instrumentation. Use them in
noinstr code.

Inline a couple more functions with single call sites, while at it:

mce_severity_amd_smca() has a single call-site which is noinstr so force
the inlining and fix:

  vmlinux.o: warning: objtool: mce_severity_amd.constprop.0()+0xca: call to \
	  mce_severity_amd_smca() leaves .noinstr.text section

Always inline mca_msr_reg():

     text    data     bss     dec     hex filename
  16065240        128031326       36405368        180501934       ac23dae vmlinux.before
  16065240        128031294       36405368        180501902       ac23d8e vmlinux.after

and mce_no_way_out() as the latter one is used only once, to fix:

  vmlinux.o: warning: objtool: mce_read_aux()+0x53: call to mca_msr_reg() leaves .noinstr.text section
  vmlinux.o: warning: objtool: do_machine_check()+0xc9: call to mce_no_way_out() leaves .noinstr.text section

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Acked-by: Marco Elver &lt;elver@google.com&gt;
Link: https://lore.kernel.org/r/20220204083015.17317-4-bp@alien8.de
</content>
</entry>
<entry>
<title>x86/mce: Check regs before accessing it</title>
<updated>2021-12-20T10:41:02Z</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2021-12-17T15:49:25Z</published>
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<id>urn:sha1:1acd85feba81084fcef00b73fc1601e42b77c5d8</id>
<content type='text'>
Commit in Fixes accesses pt_regs before checking whether it is NULL or
not. Make sure the NULL pointer check happens first.

Fixes: 0a5b288e85bb ("x86/mce: Prevent severity computation from being instrumented")
Reported-by: Dan Carpenter &lt;dan.carpenter@oracle.com&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Tony Luck &lt;tony.luck@intel.com&gt;
Link: https://lore.kernel.org/r/20211217102029.GA29708@kili
</content>
</entry>
<entry>
<title>x86/mce: Prevent severity computation from being instrumented</title>
<updated>2021-12-13T13:12:48Z</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2021-10-13T07:47:50Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0a5b288e85bbef5227bb6397e31fcf1d7ba9142a'/>
<id>urn:sha1:0a5b288e85bbef5227bb6397e31fcf1d7ba9142a</id>
<content type='text'>
Mark all the MCE severity computation logic noinstr and allow
instrumentation when it "calls out".

Fixes

  vmlinux.o: warning: objtool: do_machine_check()+0xc5d: call to mce_severity() leaves .noinstr.text section

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lore.kernel.org/r/20211208111343.8130-7-bp@alien8.de
</content>
</entry>
<entry>
<title>x86/mce: Use mce_rdmsrl() in severity checking code</title>
<updated>2021-12-13T13:12:08Z</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2021-10-05T22:55:38Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=88f66a42353717e7fac31caf04f0acd2d7fbbf54'/>
<id>urn:sha1:88f66a42353717e7fac31caf04f0acd2d7fbbf54</id>
<content type='text'>
MCA has its own special MSR accessors. Use them.

No functional changes.

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lore.kernel.org/r/20211208111343.8130-4-bp@alien8.de
</content>
</entry>
<entry>
<title>Merge tag 'ras_core_for_v5.16_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip</title>
<updated>2021-11-01T22:12:04Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2021-11-01T22:12:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=158405e888133f89dc9ec3e179c33544acdcf22a'/>
<id>urn:sha1:158405e888133f89dc9ec3e179c33544acdcf22a</id>
<content type='text'>
Pull RAS updates from Borislav Petkov:

 - Get rid of a bunch of function pointers used in MCA land in favor of
   normal functions. This is in preparation of making the MCA code
   noinstr-aware

 - When the kernel copies data from user addresses and it encounters a
   machine check, a SIGBUS is sent to that process. Change this action
   to either an -EFAULT which is returned to the user or a short write,
   making the recovery action a lot more user-friendly

* tag 'ras_core_for_v5.16_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Sort mca_config members to get rid of unnecessary padding
  x86/mce: Get rid of the -&gt;quirk_no_way_out() indirect call
  x86/mce: Get rid of msr_ops
  x86/mce: Get rid of machine_check_vector
  x86/mce: Get rid of the mce_severity function pointer
  x86/mce: Drop copyin special case for #MC
  x86/mce: Change to not send SIGBUS error during copy from user
</content>
</entry>
<entry>
<title>x86/mce: Get rid of the mce_severity function pointer</title>
<updated>2021-09-23T09:03:51Z</updated>
<author>
<name>Borislav Petkov</name>
<email>bp@suse.de</email>
</author>
<published>2021-09-01T15:02:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=631adc7b0bbaa1333fc39f0dca5e7584f51d86c9'/>
<id>urn:sha1:631adc7b0bbaa1333fc39f0dca5e7584f51d86c9</id>
<content type='text'>
Turn it into a normal function which calls an AMD- or Intel-specific
variant depending on the CPU it runs on.

No functional changes.

Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Reviewed-by: Tony Luck &lt;tony.luck@intel.com&gt;
Link: https://lkml.kernel.org/r/20210922165101.18951-2-bp@alien8.de
</content>
</entry>
<entry>
<title>x86/extable: Remove EX_TYPE_FAULT from MCE safe fixups</title>
<updated>2021-09-13T16:23:00Z</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2021-09-08T13:29:24Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0c2e62ba04cd0b7194b380bae4fc35c45bb2e46e'/>
<id>urn:sha1:0c2e62ba04cd0b7194b380bae4fc35c45bb2e46e</id>
<content type='text'>
Now that the MC safe copy and FPU have been converted to use the MCE safe
fixup types remove EX_TYPE_FAULT from the list of types which MCE considers
to be safe to be recovered in kernel.

This removes the SGX exception handling of ENCLS from the #MC safe
handling, but according to the SGX wizards the current SGX implementations
cannot survive #MC on ENCLS:

  https://lore.kernel.org/r/YS+upEmTfpZub3s9@google.com

The code relies on the trap number being stored if ENCLS raised an
exception. That's still working, but it does no longer trick the MCE code
into assuming that #MC is handled correctly for ENCLS.

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Borislav Petkov &lt;bp@suse.de&gt;
Link: https://lkml.kernel.org/r/20210908132525.445255957@linutronix.de
</content>
</entry>
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