linux-dev/drivers/bus/mhi/host, branch linus/master

Merge tag 'mhi-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi into char-work-next

2022-05-19T14:55:13Z

Manivannan writes: MHI changes for v5.19 MHI Host -------- Support for new modems: - Foxconn Cinterion MV32-WA/MV32-WB based on SDX62/SDX65 - Telit FN980 v1 based on SDX55 - Telit FN990 based on SDX65 - Foxconn T99W373/T99W368 based on SDX62/SDX65 Core changes: - During the recycle of event ring elements, compute the ctxt_wp based on the local cached value instead of reading from shared memory. This is to prevent the possible corruption of the ctxt_wp as some of the endpoint devices could modify the value in shared memory. - Add sysfs support for resetting the endpoint based on the MHI spec. The MHI spec allows the host to hard reset the device in the case of an unrecoverable error and all other reset mechanisms have failed. - During MHI shutdown, wait for the endpoint device to enter the ready state post reset before proceeding. This is to avoid a possible race where host would remove the interrupt handler and device will send ready state interrupt, resulting in IOMMU fault. - Bail out updating the MHI register if the read has failed during read/modify/write. - Use mhi_write_reg() instead of mhi_write_reg_field() for writing the whole register fields in mhi_init_mmio(). MAINTAINERS change: - Since Qualcomm has moved the email domain for its employess from codeaurora domain to quicinc, update the same for Hemant. * tag 'mhi-for-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi: (29 commits) bus: mhi: host: Add support for Foxconn T99W373 and T99W368 bus: mhi: host: pci_generic: add Telit FN990 bus: mhi: host: pci_generic: add Telit FN980 v1 hardware revision bus: mhi: host: Add support for Cinterion MV32-WA/MV32-WB bus: mhi: host: Optimize and update MMIO register write method bus: mhi: host: Bail on writing register fields if read fails bus: mhi: host: Wait for ready state after reset bus: mhi: host: Add soc_reset sysfs bus: mhi: host: pci_generic: Sort mhi_pci_id_table based on the PID bus: mhi: host: Use cached values for calculating the shared write pointer MAINTAINERS: Update Hemant's email id bus: mhi: ep: Add uevent support for module autoloading bus: mhi: ep: Add support for suspending and resuming channels bus: mhi: ep: Add support for queueing SKBs to the host bus: mhi: ep: Add support for processing channel rings bus: mhi: ep: Add support for reading from the host bus: mhi: ep: Add support for processing command rings bus: mhi: ep: Add support for handling SYS_ERR condition bus: mhi: ep: Add support for handling MHI_RESET bus: mhi: ep: Add support for powering down the MHI endpoint stack ...

bus: mhi: host: Add support for Foxconn T99W373 and T99W368

2022-05-10T05:40:56Z

Product's enumeration align with previous Foxconn SDX55, so T99W373(SDX62)/T99W368(SDX65) would use the same config as Foxconn SDX55. Remove fw and edl for this new commit. Signed-off-by: Slark Xiao Reviewed-by: Manivannan Sadhasivam Reviewed-by: Loic Poulain Link: https://lore.kernel.org/r/20220503024349.4486-1-slark_xiao@163.com Signed-off-by: Manivannan Sadhasivam

bus: mhi: host: pci_generic: add Telit FN990

2022-05-10T05:40:44Z

Add Telit FN990: 01:00.0 Unassigned class [ff00]: Qualcomm Device 0308 Subsystem: Device 1c5d:2010 Signed-off-by: Daniele Palmas Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20220502112036.443618-1-dnlplm@gmail.com [mani: Added "host" to the subject] Signed-off-by: Manivannan Sadhasivam

bus: mhi: host: pci_generic: add Telit FN980 v1 hardware revision

2022-05-10T05:40:14Z

Add Telit FN980 v1 hardware revision: 01:00.0 Unassigned class [ff00]: Qualcomm Device [17cb:0306] Subsystem: Device [1c5d:2000] Signed-off-by: Daniele Palmas Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20220427072648.17635-1-dnlplm@gmail.com [mani: Added "host" to the subject] Signed-off-by: Manivannan Sadhasivam

bus: mhi: replace snprintf with sysfs_emit

2022-05-09T13:41:01Z

Fix following coccicheck warning: ./drivers/bus/mhi/host/init.c:89:8-16: WARNING: use scnprintf or sprintf Use sysfs_emit and sysfs_emit_at instead of snprintf. Reviewed-by: Kees Cook Reviewed-by: Manivannan Sadhasivam Signed-off-by: Wan Jiabing Link: https://lore.kernel.org/r/20220426125902.681258-1-wanjiabing@vivo.com Signed-off-by: Greg Kroah-Hartman

bus: mhi: host: Add support for Cinterion MV32-WA/MV32-WB

2022-04-23T13:36:58Z

MV32-WA is designed based on Qualcomm SDX62, and MV32-WB is designed based on QUalcomm SDX65. Both products' enumeration would align with previous product MV31-W.So we merge MV31 and MV32 to MV3X for some common settings. Signed-off-by: Slark Xiao Reviewed-by: Loic Poulain Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/20220421092141.3984-1-slark_xiao@163.com [mani: removed the fixes tag that's not needed] Signed-off-by: Manivannan Sadhasivam

bus: mhi: host: Optimize and update MMIO register write method

2022-04-23T13:27:32Z

As of now, MMIO writes done after ready state transition use the mhi_write_reg_field() API even though the whole register is being written in most cases. Optimize this process by using mhi_write_reg() API instead for those writes and use the mhi_write_reg_field() API for MHI config registers only. Signed-off-by: Bhaumik Bhatt Signed-off-by: Jeffrey Hugo Reviewed-by: Hemant Kumar Reviewed-by: Jeffrey Hugo Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1650304226-11080-3-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam

bus: mhi: host: Bail on writing register fields if read fails

2022-04-23T13:27:32Z

Helper API to write register fields relies on successful reads of the register/address prior to the write. Bail out if a failure is seen when reading the register before the actual write is performed. Signed-off-by: Bhaumik Bhatt Signed-off-by: Jeffrey Hugo Reviewed-by: Hemant Kumar Reviewed-by: Jeffrey Hugo Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1650304226-11080-2-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam

bus: mhi: host: Wait for ready state after reset

2022-04-23T13:27:32Z

After the device has signaled the end of reset by clearing the reset bit, it will automatically reinit MHI and the internal device structures. Once That is done, the device will signal it has entered the ready state. Signaling the ready state involves sending an interrupt (MSI) to the host which might cause IOMMU faults if it occurs at the wrong time. If the controller is being powered down, and possibly removed, then the reset flow would only wait for the end of reset. At which point, the host and device would start a race. The host may complete its reset work, and remove the interrupt handler, which would cause the interrupt to be disabled in the IOMMU. If that occurs before the device signals the ready state, then the IOMMU will fault since it blocked an interrupt. While harmless, the fault would appear like a serious issue has occurred so let's silence it by making sure the device hits the ready state before the host completes its reset processing. Signed-off-by: Jeffrey Hugo Reviewed-by: Hemant Kumar Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1650302562-30964-1-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam

bus: mhi: host: Add soc_reset sysfs

2022-04-23T13:27:32Z

The MHI bus supports a standardized hardware reset, which is known as the "SoC Reset". This reset is similar to the reset sysfs for PCI devices - a hardware mechanism to reset the state back to square one. The MHI SoC Reset is described in the spec as a reset of last resort. If some unrecoverable error has occurred where other resets have failed, SoC Reset is the "big hammer" that ungracefully resets the device. This is effectivly the same as yanking the power on the device, and reapplying it. However, depending on the nature of the particular issue, the underlying transport link may remain active and configured. If the link remains up, the device will flag a MHI system error early in the boot process after the reset is executed, which allows the MHI bus to process a fatal error event, and clean up appropiately. While the SoC Reset is generally intended as a means of recovery when all else has failed, it can be useful in non-error scenarios. For example, if the device loads firmware from the host filesystem, the device may need to be fully rebooted inorder to pick up the new firmware. In this scenario, the system administrator may use the soc_reset sysfs to cause the device to pick up the new firmware that the admin placed on the filesystem. Signed-off-by: Jeffrey Hugo Reviewed-by: Bhaumik Bhatt Reviewed-by: Manivannan Sadhasivam Link: https://lore.kernel.org/r/1650302327-30439-1-git-send-email-quic_jhugo@quicinc.com Signed-off-by: Manivannan Sadhasivam