<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/char/hw_random/Kconfig, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/char/hw_random/Kconfig?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/char/hw_random/Kconfig?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-07-11T02:11:00Z</updated>
<entry>
<title>hwrng: bcm2835: bcmbca: Replace ARCH_BCM_63XX with ARCH_BCMBCA</title>
<updated>2022-07-11T02:11:00Z</updated>
<author>
<name>William Zhang</name>
<email>william.zhang@broadcom.com</email>
</author>
<published>2022-07-07T06:57:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=aa6c9ae616b8fd44980c9236f87ce6da076f1ee6'/>
<id>urn:sha1:aa6c9ae616b8fd44980c9236f87ce6da076f1ee6</id>
<content type='text'>
Prepare for the BCM63138 ARCH_BCM_63XX migration to ARCH_BCMBCA. Make
HW_RANDOM_BCM2835 depending on ARCH_BCMBCA.

Signed-off-by: William Zhang &lt;william.zhang@broadcom.com&gt;
Acked-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
Signed-off-by: Florian Fainelli &lt;f.fainelli@gmail.com&gt;
</content>
</entry>
<entry>
<title>hwrng: cn10k - Enable compile testing</title>
<updated>2022-05-06T10:16:55Z</updated>
<author>
<name>Herbert Xu</name>
<email>herbert@gondor.apana.org.au</email>
</author>
<published>2022-04-29T05:37:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=25dfae684031f292034a0f42155090df6309f152'/>
<id>urn:sha1:25dfae684031f292034a0f42155090df6309f152</id>
<content type='text'>
This patch enables COMPILE_TEST for cn10k.

Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>Revert "hwrng: mpfs - Enable COMPILE_TEST"</title>
<updated>2022-04-26T09:42:36Z</updated>
<author>
<name>Herbert Xu</name>
<email>herbert@gondor.apana.org.au</email>
</author>
<published>2022-04-26T09:42:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c6d3ffae0d3229e06097f2790f459c96fca5e367'/>
<id>urn:sha1:c6d3ffae0d3229e06097f2790f459c96fca5e367</id>
<content type='text'>
This reverts commit 6a71277ce91e4766ebe9a5f6725089c80d043ba2.

The underlying option POLARFIRE_SOC_SYS_CTRL already supports
COMPILE_TEST so there is no need for this.  What's more, if
we force this option on without the underlying option it fails
to build.

Reported-by: kernel test robot &lt;lkp@intel.com&gt;
Reported-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>hwrng: mpfs - Enable COMPILE_TEST</title>
<updated>2022-04-21T09:53:55Z</updated>
<author>
<name>Herbert Xu</name>
<email>herbert@gondor.apana.org.au</email>
</author>
<published>2022-04-15T08:37:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=6a71277ce91e4766ebe9a5f6725089c80d043ba2'/>
<id>urn:sha1:6a71277ce91e4766ebe9a5f6725089c80d043ba2</id>
<content type='text'>
The dependency on HW_RANDOM is redundant so this patch removes it.
As this driver seems to cross-compile just fine we could also enable
COMPILE_TEST.

Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com
Reviewed-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>hwrng: mpfs - add polarfire soc hwrng support</title>
<updated>2022-04-15T08:34:28Z</updated>
<author>
<name>Conor Dooley</name>
<email>conor.dooley@microchip.com</email>
</author>
<published>2022-04-08T10:09:12Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=716a757c83ad6208a743dd8fb1577055d0867ee8'/>
<id>urn:sha1:716a757c83ad6208a743dd8fb1577055d0867ee8</id>
<content type='text'>
Add a driver to access the hardware random number generator on the
Polarfire SoC. The hwrng can only be accessed via the system controller,
so use the mailbox interface the system controller exposes to access the
hwrng.

Signed-off-by: Conor Dooley &lt;conor.dooley@microchip.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>hwrng: cavium - HW_RANDOM_CAVIUM should depend on ARCH_THUNDER</title>
<updated>2022-01-31T00:21:37Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2022-01-12T14:05:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ab7d88549e2f7ae116afd303f32e1950cb790a1d'/>
<id>urn:sha1:ab7d88549e2f7ae116afd303f32e1950cb790a1d</id>
<content type='text'>
The Cavium ThunderX Random Number Generator is only present on Cavium
ThunderX SoCs, and not available as an independent PCIe endpoint.  Hence
add a dependency on ARCH_THUNDER, to prevent asking the user about this
driver when configuring a kernel without Cavium Thunder SoC  support.

Fixes: cc2f1908c6b8f625 ("hwrng: cavium - Add Cavium HWRNG driver for ThunderX SoC.")
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>Merge tag 'mips_5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux</title>
<updated>2022-01-14T14:08:36Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-01-14T14:08:36Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3fb561b1e0bf4c75bc5f4d799845b08fa5ab3853'/>
<id>urn:sha1:3fb561b1e0bf4c75bc5f4d799845b08fa5ab3853</id>
<content type='text'>
Pull MIPS updates from Thomas Bogendoerfer:

 - add support for more BCM47XX based devices

 - add MIPS support for brcmstb PCIe controller

 - add Loongson 2K1000 reset driver

 - remove board support for rbtx4938/rbtx4939

 - remove support for TX4939 SoCs

 - fixes and cleanups

* tag 'mips_5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (59 commits)
  MIPS: ath79: drop _machine_restart again
  PCI: brcmstb: Augment driver for MIPs SOCs
  MIPS: bmips: Remove obsolete DMA mapping support
  MIPS: bmips: Add support PCIe controller device nodes
  dt-bindings: PCI: Add compatible string for Brcmstb 74[23]5 MIPs SOCs
  MIPS: compressed: Fix build with ZSTD compression
  MIPS: BCM47XX: Add support for Netgear WN2500RP v1 &amp; v2
  MIPS: BCM47XX: Add support for Netgear R6300 v1
  MIPS: BCM47XX: Add LEDs and buttons for Asus RTN-10U
  MIPS: BCM47XX: Add board entry for Linksys WRT320N v1
  MIPS: BCM47XX: Define Linksys WRT310N V2 buttons
  MIPS: Remove duplicated include in local.h
  MIPS: retire "asm/llsc.h"
  MIPS: rework local_t operation on MIPS64
  MIPS: fix local_{add,sub}_return on MIPS64
  mips/pci: remove redundant ret variable
  MIPS: Loongson64: Add missing of_node_put() in ls2k_reset_init()
  MIPS: new Kconfig option ZBOOT_LOAD_ADDRESS
  MIPS: enable both vmlinux.gz.itb and vmlinuz for generic
  MIPS: signal: Return immediately if call fails
  ...
</content>
</entry>
<entry>
<title>MIPS: TXX9: Remove TX4939 SoC support</title>
<updated>2022-01-02T13:12:03Z</updated>
<author>
<name>Thomas Bogendoerfer</name>
<email>tsbogend@alpha.franken.de</email>
</author>
<published>2021-11-30T16:45:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=fc5bb239d5b3500d034559e0c5ecb67bbae69de7'/>
<id>urn:sha1:fc5bb239d5b3500d034559e0c5ecb67bbae69de7</id>
<content type='text'>
After removal of RBTX4939 board support remove code for the TX4939 SoC.

Signed-off-by: Thomas Bogendoerfer &lt;tsbogend@alpha.franken.de&gt;
Tested-by: Geert Uytterhoeven &lt;geert@linux-m68k.org&gt;
</content>
</entry>
<entry>
<title>hwrng: cn10k - Add random number generator support</title>
<updated>2021-12-24T03:18:22Z</updated>
<author>
<name>Sunil Goutham</name>
<email>sgoutham@marvell.com</email>
</author>
<published>2021-12-14T10:51:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=38e9791a02090414d1e3433549001689cad71098'/>
<id>urn:sha1:38e9791a02090414d1e3433549001689cad71098</id>
<content type='text'>
CN10K series of silicons support true random number
generators. This patch adds support for the same. Also
supports entropy health status checking.

Signed-off-by: Sunil Goutham &lt;sgoutham@marvell.com&gt;
Signed-off-by: Bharat Bhushan &lt;bbhushan2@marvell.com&gt;
Signed-off-by: Joseph Longever &lt;jlongever@marvell.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>hwrng: cavium - Check health status while reading random data</title>
<updated>2021-11-20T04:02:07Z</updated>
<author>
<name>Sunil Goutham</name>
<email>sgoutham@marvell.com</email>
</author>
<published>2021-10-29T17:19:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=680efb33546be8960ccbb2f4e0e43034d9c93b30'/>
<id>urn:sha1:680efb33546be8960ccbb2f4e0e43034d9c93b30</id>
<content type='text'>
This RNG device is present on Marvell OcteonTx2 silicons as well and
also provides entropy health status.

HW continuously checks health condition of entropy and reports
faults. Fault is in terms of co-processor cycles since last fault
detected. This doesn't get cleared and only updated when new fault
is detected. Also there are chances of detecting false positives.
So to detect a entropy failure SW has to check if failures are
persistent ie cycles elapsed is frequently updated by HW.

This patch adds support to detect health failures using below algo.
1. Consider any fault detected before 10ms as a false positive and ignore.
   10ms is chosen randomly, no significance.
2. Upon first failure detection make a note of cycles elapsed and when this
   error happened in realtime (cntvct).
3. Upon subsequent failure, check if this is new or a old one by comparing
   current cycles with the ones since last failure. cycles or time since
   last failure is calculated using cycles and time info captured at (2).

HEALTH_CHECK status register is not available to VF, hence had to map
PF registers. Also since cycles are in terms of co-processor cycles,
had to retrieve co-processor clock rate from RST device.

Signed-off-by: Sunil Goutham &lt;sgoutham@marvell.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
