linux-dev/drivers/clk/meson/Makefile, branch master

clk: meson: add a driver for the Meson8/8b/8m2 DDR clock controller

2019-12-11T13:06:29Z

The Meson8/Meson8b/Meson8m2 SoCs embed a DDR clock controller in the MMCBUS registers. There is no public documentation, but the u-boot GPL sources from the Amlogic BSP show that the DDR clock controller is identical on all three SoCs: #define CFG_DDR_CLK 792 #define CFG_PLL_M (((CFG_DDR_CLK/12)*12)/24) #define CFG_PLL_N 1 #define CFG_PLL_OD 1 // from set_ddr_clock: t_ddr_pll_cntl= (CFG_PLL_OD << 16)|(CFG_PLL_N<<9)|(CFG_PLL_M<<0) writel(timing_reg->t_ddr_pll_cntl|(1<<29),AM_DDR_PLL_CNTL); writel(readl(AM_DDR_PLL_CNTL) & (~(1<<29)),AM_DDR_PLL_CNTL); // from hx_ddr_power_down_enter: shut down DDR PLL writel(readl(AM_DDR_PLL_CNTL)|(1<<30),AM_DDR_PLL_CNTL); do { ... } while((readl(AM_DDR_PLL_CNTL)&(1<<31))==0) This translates to: - AM_DDR_PLL_CNTL[29] is the reset bit - AM_DDR_PLL_CNTL[30] is the enable bit - AM_DDR_PLL_CNTL[31] is the lock bit - AM_DDR_PLL_CNTL[8:0] is the m value (assuming the width is 9 bits based on the start of the n value) - AM_DDR_PLL_CNTL[13:9] is the n value (assuming the width is 5 bits based on the start of the od) - AM_DDR_PLL_CNTL[17:16] is the od (assuming the width is 2 bits based on other PLLs on this SoC) Add a driver for this PLL setup because it's used as one of the inputs of the audio clocks. There may be more clocks inside that clock controller - those can be added in subsequent patches. Signed-off-by: Martin Blumenstingl Signed-off-by: Jerome Brunet

clk: meson: add g12a cpu dynamic divider driver

2019-08-09T10:10:03Z

Add a clock driver for the cpu dynamic divider, this divider needs to have a flag set before setting the divider value then removed while writing the new value to the register. This drivers implements this behavior and will be used essentially on the Amlogic G12A and G12B SoCs for cpu clock trees. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Jerome Brunet

clk: meson: remove clk input helper

2019-07-29T10:42:49Z

The clk input function which allows clock controllers to register a bypass clock from a clock producer is no longer needed anymore since meson clock controllers have migrated to a new parent allocation method. Signed-off-by: Alexandre Mergnat Signed-off-by: Jerome Brunet

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21T08:50:46Z

Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman

clk: meson: Add G12A AO Clock + Reset Controller

2019-02-13T08:49:32Z

Add the Amlogic G12A AO Clock and Reset controller driver handling generation of Always-On clocks : - AO Clocks and Reset for Always-On modules - 32K Generation for USB and CEC - SAR ADC controller clock Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Acked-by: Jerome Brunet Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com

clk: meson: factorise meson64 peripheral clock controller drivers

2019-02-04T08:52:11Z

The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com

clk: meson: g12a: add peripheral clock controller

2019-02-04T08:52:11Z

Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com

clk: meson: rework and clean drivers dependencies

2019-02-02T16:43:32Z

Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com

clk: meson: gxbb-ao: replace cec-32k with the dual divider

2019-01-07T14:21:22Z

Replace the cec-32k clock of gxbb-ao with the simpler dual divider driver. The dual divider implements only the dividing part. All the other bits are now exposed using simple elements, such as gates and muxes Signed-off-by: Jerome Brunet Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181221160239.26265-5-jbrunet@baylibre.com

clk: meson: add dual divider clock driver

2019-01-07T14:21:01Z

Add the dual divider driver. This special divider make a weighted average between 2 dividers to reach fractional divider values. Signed-off-by: Jerome Brunet Acked-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20181221160239.26265-4-jbrunet@baylibre.com