linux-dev/drivers/clk/meson/axg.c, branch linus/master

clk: meson: axg: Remove MIPI enable clock gate

2021-02-09T12:32:59Z

On AXG platforms HHI_MIPI_CNTL0 is part of the MIPI/PCIe analog PHY region and is not related to clock one and can be removed from it. Signed-off-by: Remi Pommarel Signed-off-by: Jerome Brunet

clk: meson: enable building as modules

2020-11-23T08:08:23Z

Make it possible to build all clk drivers as modules, but default remains built-in. No functional changes. Signed-off-by: Kevin Hilman Signed-off-by: Jerome Brunet Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20201118191405.36798-1-khilman@baylibre.com

clk: meson: axg: add MIPI DSI Host clock

2020-11-23T08:08:22Z

This adds the MIPI DSI Host clock, used to measure the signal timings (ENC VSYNC or DW-MIPI-DSI eDPI timings). Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200915124553.8056-5-narmstrong@baylibre.com

clk: meson: axg: add Video Clocks

2020-11-23T08:08:22Z

Add the clocks entries used in the video clock path, the clock path is doubled to permit having different synchronized clocks for different parts of the video pipeline. The AXG only has a single ENCL CTS clock and even if VCLK exist along VCLK2, only VCLK2 is used since it clocks the MIPI DSI IP directly. All dividers are flagged with CLK_GET_RATE_NOCACHE, and all gates are flagged with CLK_IGNORE_UNUSED since they are currently directly handled by the Meson DRM Driver. Once the DRM Driver is fully migrated to using the Common Clock Framework to handle the video clock tree, the CLK_GET_RATE_NOCACHE and CLK_IGNORE_UNUSED will be dropped. Signed-off-by: Neil Armstrong Signed-off-by: Jerome Brunet Link: https://lore.kernel.org/r/20200915124553.8056-4-narmstrong@baylibre.com

clk: meson: clk-regmap: migrate to new parent description method

2019-07-29T10:42:49Z

This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (ie. when all clocks are local to the controller) and use .parent_data otherwise. Signed-off-by: Alexandre Mergnat Signed-off-by: Jerome Brunet

clk: meson: axg: migrate to the new parent description method

2019-07-29T10:42:48Z

clk: meson: axg: spread spectrum is on mpll2

2019-05-20T10:18:55Z

After testing, it appears that the SSEN bit controls the spread spectrum function on MPLL2, not MPLL0. Fixes: 78b4af312f91 ("clk: meson-axg: add clock controller drivers") Signed-off-by: Jerome Brunet

clk: meson: factorise meson64 peripheral clock controller drivers

2019-02-04T08:52:11Z

The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com

clk: meson: rework and clean drivers dependencies

2019-02-02T16:43:32Z

Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com

clk: meson: axg: claim clock controller input clock from DT

2019-01-18T09:51:14Z

Instead of relying on a fixed name for the xtal clock, claim the controller input clock trough DT. Signed-off-by: Jerome Brunet Reviewed-by: Neil Armstrong Signed-off-by: Neil Armstrong Link: https://lkml.kernel.org/r/20190116175435.4990-3-jbrunet@baylibre.com