linux-dev/drivers/clk/microchip, branch master

clk: microchip: add PolarFire SoC fabric clock support

2022-09-14T07:57:07Z

Add a driver to support the PLLs in PolarFire SoC's Clock Conditioning Circuitry, an instance of which is located in each ordinal corner of the FPGA. Only get_rate() is supported as these clocks are intended to be statically configured by the FPGA design. Currently, the DLLs are not supported by this driver. For more information on the hardware, see "PolarFire SoC FPGA Clocking Resources" in the link below. Link: https://onlinedocs.microchip.com/pr/GUID-8F0CC4C0-0317-4262-89CA-CE7773ED1931-en-US-1/index.html Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220908143651.1252601-5-conor.dooley@microchip.com

clk: microchip: mpfs: update module authorship & licencing

2022-09-14T07:57:07Z

Padmarao wrote the driver in its original, pre upstream form. Daire & myself have been responsible for getting it upstreamable and subsequent development. Move Daire out of the blurb & into a MODULE_AUTHOR entry & add entries for myself and Padmarao. While we are at it, convert the MODULE_LICENSE field to its preferred form of "GPL". Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-15-conor.dooley@microchip.com

clk: microchip: mpfs: convert periph_clk to clk_gate

2022-09-14T07:57:07Z

With the reset code moved to the recently added reset controller, there is no need for custom ops any longer. Remove the custom ops and the custom struct by converting to a clk_gate. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-14-conor.dooley@microchip.com

clk: microchip: mpfs: convert cfg_clk to clk_divider

2022-09-14T07:57:06Z

The cfg_clk struct is now just a redefinition of the clk_divider struct with custom implentations of the ops, that implement an extra level of redirection. Remove the custom struct and replace it with clk_divider. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-13-conor.dooley@microchip.com

clk: microchip: mpfs: delete 2 line mpfs_clk_register_foo()

2022-09-14T07:57:06Z

The register functions are now comprised of only a single operation each and no longer add anything to the driver. Delete them. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-12-conor.dooley@microchip.com

clk: microchip: mpfs: simplify control reg access

2022-09-14T07:57:06Z

The control reg addresses are known when the clocks are registered, so we can, instead of assigning a base pointer to the structs, assign the control reg addresses directly. Accordingly, remove the interim variables used during reads/writes to those registers. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-11-conor.dooley@microchip.com

clk: microchip: mpfs: move id & offset out of clock structs

2022-09-14T07:57:06Z

The id and offset are the only thing differentiating the clock structs from "regular" clock structures. On the pretext of converting to more normal structures, move the id and offset out of the clock structs and into the hw structs instead. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-10-conor.dooley@microchip.com

clk: microchip: mpfs: add MSS pll's set & round rate

2022-09-14T07:57:06Z

The MSS pll is not a fixed frequency clock, so add set() & round_rate() support. Control is limited to a 7 bit output divider as other devices on the FPGA occupy the other three outputs of the PLL & prevent changing the multiplier. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-9-conor.dooley@microchip.com

clk: microchip: mpfs: add reset controller

2022-09-14T07:55:17Z

Add a reset controller to PolarFire SoC's clock driver. This reset controller is registered as an aux device and read/write functions exported to the drivers namespace so that the reset controller can access the peripheral device reset register. Reviewed-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Claudiu Beznea Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-5-conor.dooley@microchip.com

clk: microchip: mpfs: make the rtc's ahb clock critical

2022-09-14T07:45:52Z

The onboard RTC's AHB bus clock must be kept running as the RTC will stop & lose track of time if the AHB interface clock is disabled. Fixes: 635e5e73370e ("clk: microchip: Add driver for Microchip PolarFire SoC") Signed-off-by: Conor Dooley Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220909123123.2699583-3-conor.dooley@microchip.com