linux-dev/drivers/clk/mmp, branch master

clk: mmp: pxa168: control shared SDH bits with separate clock

2022-09-30T20:34:07Z

The PXA168 has a peculiar setup with the AXI clock enable control for the SDHC controllers. The bits in the SDH0 register control the AXI clock enable for both SDH0 and SDH1. Likewise, the bits in the SDH2 register control both SDH2 and SDH3. This is modeled with two new parentless clocks that control the shared bits. Previously, SDH0 had to be enabled in order for SDH1 to be used, and when SDH1 was enabled, unused bits in the SDH1 register were being controlled. This fixes those issues. A future commit will add support for these new shared clocks to be enabled by the PXA168 SDHC driver. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-13-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: add clocks for SDH2 and SDH3

2022-09-30T20:34:07Z

The PXA168 has four SDHC peripherals. This commit adds the last two. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-11-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: fix GPIO clock enable bits

2022-09-30T20:34:06Z

According to the datasheet, only bit 0 of APBC_GPIO should be controlled for the clock enable. Bit 1 is marked as reserved (always write 0). Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-9-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: add muxes for more peripherals

2022-09-30T20:34:06Z

The TWSI, KPC, PWM, and DFC peripherals didn't have their muxes modeled in the code, but the PXA168 datasheet shows that they are indeed muxed: - TWSI can be 31.2 MHz or 62.4 MHz - KPC can be 32 kHz, 16 kHz, or 26 MHz - PWM can be 13 MHz or 32 kHz - DFC can be 156 MHz or 78 MHz Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-8-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: fix incorrect parent clocks

2022-09-30T20:34:06Z

The UART, SDHC, LCD, and CCIC peripherals' muxed parent clocks didn't match the information provided by the PXA168 datasheet: - The UART clocks can be 58.5 MHz or the UART PLL. Previously, the first mux option was being calculated as 117 MHz, confirmed on hardware to be incorrect. - The SDHC clocks can be 48 MHz, 52 MHz, or 78 MHz. Previously, 48 MHz and 52 MHz were swapped. 78 MHz wasn't listed as an option. - The LCD clock can be 624 MHz or 312 Mhz. Previously, it was being calculated as 312 MHz or 52 MHz. - The CCIC clock can be 156 MHz or 78 MHz. Previously, it was being calculated as 312 MHz or 52 MHz. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-7-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: fix const-correctness

2022-09-30T20:34:06Z

While working on this series of patches, checkpatch recommended that an extra const should be added to the mux parent arrays. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-6-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: add new clocks for peripherals

2022-09-30T20:34:06Z

This commit adds three new clocks that previously didn't exist, but are needed in order to match the clock parenting as described in the PXA168 datasheet. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-5-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: fix incorrect dividers

2022-09-30T20:34:06Z

These two clocks had multipliers and dividers that didn't match their names. A subsequent commit goes through all of the existing peripherals and ensure the correct clocks are being used everywhere. Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-3-doug@schmorgal.com Signed-off-by: Stephen Boyd

clk: mmp: pxa168: add additional register defines

2022-09-30T20:34:06Z

In preparation for adding additional peripherals over time, this commit adds a bunch of extra APBC_* defines based on information from the datasheet. It also reorganizes the list of defines to be ordered sequentially by address (grouped by type). Signed-off-by: Doug Brown Link: https://lore.kernel.org/r/20220612192937.162952-2-doug@schmorgal.com Signed-off-by: Stephen Boyd

treewide: Replace GPLv2 boilerplate/reference with SPDX - gpl-2.0_56.RULE (part 2)

2022-06-10T12:51:35Z

Based on the normalized pattern: this file is licensed under the terms of the gnu general public license version 2 this program is licensed as is without any warranty of any kind whether express or implied extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference. Signed-off-by: Thomas Gleixner Signed-off-by: Greg Kroah-Hartman