linux-dev/drivers/clk/qcom/Makefile, branch master

clk: qcom: Add global clock controller driver for SM6375

2022-09-28T03:25:57Z

Add support for the global clock controller found on SM6375. Signed-off-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220921001303.56151-3-konrad.dybcio@somainline.org

clk: qcom: Add SC8280XP GPU clock controller

2022-09-27T17:07:30Z

Add driver for the GPU clock controller in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson Reviewed-by: Konrad Dybcio [bjorn: Included kernel.h and lower-cased hex numbers] Signed-off-by: Bjorn Andersson Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220926173025.4747-3-quic_bjorande@quicinc.com

clk: qcom: Add support for Display Clock Controller on SM8450

2022-09-27T03:17:14Z

Add support for the dispcc on Qualcomm SM8450 platform. Signed-off-by: Dmitry Baryshkov Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220908222850.3552050-4-dmitry.baryshkov@linaro.org

clk: qcom: Add display clock controller driver for SM6115

2022-09-27T03:17:13Z

Add support for the display clock controller found in SM6115/SM4250 based devices. This clock controller feeds the Multimedia Display SubSystem (MDSS). This driver is based upon one submitted for QCM2290. Signed-off-by: Adam Skladowski Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220911164635.182973-3-a39.skl@gmail.com

clk: qcom: Add driver for MSM8909 GCC

2022-09-14T03:07:25Z

The Global Clock Controller (GCC) in the MSM8909 SoC provides clocks, resets and power domains for the various hardware blocks in the SoC. Add a driver for it to make it possible to enable additional functionality for the SoC. Work on this driver was originally started independently by Dominik, I picked it up and added missing clocks/resets, as well as various cleanup to bring it into shape for mainline. Co-developed-by: Dominik Kobinski Signed-off-by: Dominik Kobinski Signed-off-by: Stephan Gerhold Reviewed-by: Konrad Dybcio Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706134132.3623415-3-stephan.gerhold@kernkonzept.com

clk: qcom: add support for SM8350 GPUCC

2022-07-06T20:20:59Z

The GPUCC manages the clocks for the Adreno GPU found on the sm8350 SoCs. Signed-off-by: Robert Foss Signed-off-by: Jonathan Marek Reviewed-by: Vinod Koul Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220706154337.2026269-3-robert.foss@linaro.org

clk: qcom: add camera clock controller driver for SM8450 SoC

2022-07-06T20:20:59Z

Add camera clock controller driver found on Qualcomm SM8450 SoC. Reviewed-by: Bjorn Andersson Signed-off-by: Vladimir Zapolskiy Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220701062744.2757931-1-vladimir.zapolskiy@linaro.org

clk: qcom: regmap: add PHY clock source implementation

2022-06-26T02:36:07Z

On recent Qualcomm platforms the QMP PIPE clocks feed into a set of muxes which must be parked to the "safe" source (bi_tcxo) when corresponding GDSC is turned off and on again. Currently this is handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src clock. However the same code sequence should be applied in the pcie-qcom endpoint, USB3 and UFS drivers. Rather than copying this sequence over and over again, follow the example of clk_rcg2_shared_ops and implement this parking in the enable() and disable() clock operations. Supplement the regmap-mux with the new clk_regmap_phy_mux type, which implements such multiplexers as a simple gate clocks. This is possible since each of these multiplexers has just two clock sources: one coming from the PHY and a reference (XO) one. If the clock is running off the from-PHY source, report it as enabled. Report it as disabled otherwise (if it uses reference source). This way the PHY will disable the pipe clock before turning off the GDSC, which in turn would lead to disabling corresponding pipe_clk_src (and thus it being parked to a safe, reference clock source). And vice versa, after enabling the GDSC the PHY will enable the pipe clock, which would cause pipe_clk_src to be switched from a safe source to the working one. Reviewed-by: Johan Hovold Tested-by: Johan Hovold Reported-by: kernel test robot Signed-off-by: Dmitry Baryshkov Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220608105238.2973600-2-dmitry.baryshkov@linaro.org

clk: qcom: add sc8280xp GCC driver

2022-05-19T21:41:32Z

Add support for the Global Clock Controller found in the Qualcomm SC8280XP platform. Signed-off-by: Bjorn Andersson Reviewed-by: Vinod Koul Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20220505025457.1693716-3-bjorn.andersson@linaro.org

clk: qcom: lpass: Add support for LPASS clock controller for SC7280

2022-04-13T02:17:42Z

The Low Power Audio subsystem core and audio clocks are required for Audio client to be able to request for the clocks and power domains. Signed-off-by: Taniya Das Reviewed-by: Stephen Boyd Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20220223172248.18877-2-tdas@codeaurora.org