linux-dev/drivers/clk/renesas/Kconfig, branch master

clk: renesas: Add RZ/V2M support using the rzg2l driver

2022-05-06T07:38:40Z

The Renesas RZ/V2M SoC is very similar to RZ/G2L, though it doesn't have any CLK_MON registers. Signed-off-by: Phil Edworthy Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20220503115557.53370-11-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: cpg-mssr: Add support for R-Car V4H

2022-04-29T10:23:39Z

Initial CPG support for R-Car V4H (r8a779g0). Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20220428135058.597586-2-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: Add support for RZ/G2UL SoC

2022-04-13T10:29:08Z

The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are not present on RZ/G2UL. This patch adds minimal clock and reset entries required to boot the system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core driver. Signed-off-by: Biju Das Reviewed-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rzg2l-cpg: Add support for RZ/V2L SoC

2022-02-10T13:34:58Z

The clock structure for RZ/V2L is almost identical to the RZ/G2L SoC. The only difference being that RZ/V2L has additional registers to control clocks and resets for the DRP-AI block. Reuse r9a07g044-cpg.c, as the clock IDs and reset IDs are the same between RZ/G2L and RZ/V2L, and add a separate r9a07g054_cpg_info to take care of the DRP-AI clocks/resets. Signed-off-by: Biju Das Signed-off-by: Lad Prabhakar Link: https://lore.kernel.org/r/20220205084006.7142-1-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/r/20220209203411.22332-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: cpg-mssr: Add support for R-Car S4-8

2021-12-08T09:05:56Z

Initial CPG support for R-Car S4-8 (r8a779f0). Inspired by patches in the BSP by LUU HOAI. Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-10-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: rcar-gen4: Introduce R-Car Gen4 CPG driver

2021-12-08T09:05:22Z

According to the official website [1], the R-Car V3U SoC is based on the R-Car Gen4 architecture. So, introduce R-Car Gen4 CPG driver. [1] https://www.renesas.com/us/en/products/automotive-products/automotive-system-chips-socs/r-car-v3u-best-class-r-car-v3u-asil-d-system-chip-automated-driving Signed-off-by: Yoshihiro Shimoda Link: https://lore.kernel.org/r/20211201073308.1003945-9-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: Make CLK_R9A06G032 invisible

2021-08-13T10:05:41Z

When configuring a kernel including support for Renesas ARM/ARM64 Socs, but excluding support for the RZ/N1D SoC, the user is always asked about the RZ/N1D clock driver. As this driver is already auto-selected when building a kernel including support for the RZ/N1D SoC, there is no need to make the CLK_R9A06G032 symbol visible, unless compile-testing. Align the symbol description with the other symbols. Signed-off-by: Geert Uytterhoeven Reviewed-by: Niklas Söderlund Link: https://lore.kernel.org/r/4f3d30c730c30546f702715ffc648922a8156703.1628672649.git.geert+renesas@glider.be

clk: renesas: Add support for R9A07G044 SoC

2021-06-10T13:46:46Z

Define the clock outputs supported by RZ/G2L (R9A07G044) SoC and bind it with RZ/G2L CPG core. Based on a patch in the BSP by Binh Nguyen . Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609153230.6967-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: Add CPG core wrapper for RZ/G2L SoC

2021-06-10T13:46:17Z

Add CPG core wrapper for RZ/G2L family. Based on a patch in the BSP by Binh Nguyen . Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das Link: https://lore.kernel.org/r/20210609153230.6967-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: r8a779a0: Add SDHI support

2021-01-12T11:35:13Z

We use the shiny new CPG library for that. Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20201227174202.40834-5-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven