linux-dev/drivers/clk/renesas, branch master

clk: renesas: r8a779g0: Fix HSCIF parent clocks

2022-10-26T10:05:36Z

As serial communication requires a clean clock signal, the High Speed Serial Communication Interfaces with FIFO (HSCIF) is clocked by a clock that is not affected by Spread Spectrum or Fractional Multiplication. Hence change the parent clocks for the HSCIF modules from the S0D3_PER clock to the SASYNCPERD1 clock (which has the same clock rate), cfr. R-Car V4H Hardware User's Manual rev. 0.54. Fixes: 0ab55cf1834177a2 ("clk: renesas: cpg-mssr: Add support for R-Car V4H") Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/b7928abc8b9f53d5b06ec8624342f449de3d24ec.1665147497.git.geert+renesas@glider.be

clk: renesas: r8a779g0: Add SASYNCPER clocks

2022-10-18T06:58:06Z

On R-Car V4H, all PLLs except PLL5 support Spread Spectrum and/or Fractional Multiplication to reduce electromagnetic interference. Add the SASYNCPER and SASYNCPERD[124] clocks, which are used as clock sources for modules that must not be affected by Spread Spectrum and/or Fractional Multiplication. Signed-off-by: Geert Uytterhoeven Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/d0f35c35e1f96c5a649ab477e7ba5d8025957cd0.1665147497.git.geert+renesas@glider.be

clk: renesas: r8a779g0: Add EtherAVB clocks

2022-09-18T12:43:51Z

Add the module clocks used by the Ethernet AVB (EtherAVB-IF) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Based on a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/e9382b0d9acc84acc2357a6921a1459f3a32240e.1662714852.git.geert+renesas@glider.be

clk: renesas: r8a779g0: Add PFC/GPIO clocks

2022-09-18T12:43:51Z

Add the module clocks used by the Pin Function Controller (PFC) and General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/cc6a22f0ad49643e17b9921b27aa9cf0a3b8d57a.1662714852.git.geert+renesas@glider.be

clk: renesas: r8a779g0: Add I2C clocks

2022-09-18T12:43:51Z

Add the module clocks used by the I2C Bus Interfaces on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/f4b94f37950f6e976b68d0b32c324fb026d8b696.1662714852.git.geert+renesas@glider.be

clk: renesas: r8a779g0: Add watchdog clock

2022-09-18T12:43:51Z

Add the module clock used by the RCLK Watchdog Timer on the Renesas R-Car V4H (R8A779G0) SoC. Extracted from a larger patch in the BSP by Kazuya Mizuguchi. Signed-off-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/a012e4449b976efbeaabebb983fa6cfc1b9329d3.1662714852.git.geert+renesas@glider.be

clk: renesas: r8a779f0: Add MSIOF clocks

2022-08-29T07:22:57Z

Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220824103515.54931-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a09g011: Add IIC clock and reset entries

2022-08-29T07:22:57Z

Add IIC groups clock and reset entries to CPG driver. IIC Group A consists of IIC0 and IIC1. IIC Group B consists of IIC2 and IIC3. To confuse things, IIC_PCLK0 is used by group A and IIC_PCLK1 is used by group B. Signed-off-by: Phil Edworthy Link: https://lore.kernel.org/r/20220819193944.337599-2-phil.edworthy@renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info

2022-08-22T07:47:36Z

Add conditional compilation for struct r9a07g044_cpg_info, so the compiler won't allocate any memory for this variable in case CONFIG_CLK_R9A07G044 is disabled. Reported-by: Pavel Machek Signed-off-by: Biju Das Link: https://lore.kernel.org/r/20220804082605.157269-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven

clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks

2022-08-22T07:47:06Z

Signed-off-by: Wolfram Sang Link: https://lore.kernel.org/r/20220726210110.1444-2-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven