linux-dev/drivers/clk/ux500, branch master

clk: ux500: fix a possible off-by-one in u8500_prcc_reset_base()

2022-05-18T20:34:03Z

Off-by-one will happen when index == ARRAY_SIZE(ur->base). Fixes: b14cbdfd467d ("clk: ux500: Add driver for the reset portions of PRCC") Signed-off-by: Hangyu Hua Link: https://lore.kernel.org/r/20220518062537.17933-1-hbh25y@gmail.com Reviewed-by: Linus Walleij Signed-off-by: Stephen Boyd

clk: ux500: Implement the missing CLKOUT clocks

2022-04-25T23:17:25Z

This implements the two missing CLKOUT clocks for the ux500 (well really U8500/DB8500) SoC. The clocks are initialized using a specific parent and divider and these are specified in the device tree, see the separate binding patch. The implementation is a bit different in that it will only create the clock in the clock framework if a user appears in the device tree, rather than it being registered upfront like most of the other clocks. This is because the clock needs parameters for source and divider from the consumer phandle for the clock to be set up properly when the clock is registered. There could be more than one user of a CLKOUT clock, but we have not seen this in practice. If this happens the framework prints and info and returns the previously registered clock. Using the clocks requires also muxing the CLKOUT1 or CLKOUT2 to the appropriate pad. In practice this is achived in a pinctrl handle in the DTS node for the device using the CLKOUT clock, so this muxing is done separately from the clock itself. Example: haptic@49 { compatible = "immersion,isa1200"; reg = <0x49>; (...) /* clkout1 from ACLK divided by 8 */ clocks = <&clkout_clk DB8500_CLKOUT_1 DB8500_CLKOUT_SRC_ACLK 8>; pinctrl-names = "default"; pinctrl-0 = <&isa1200_janice_default>; }; isa1200_janice_default: isa1200_janice { /* Bring out clkout1 on pin GPIO227 pin AH7 */ janice_mux { function = "clkout"; groups = "clkout1_a_1"; }; janice_cfg1 { pins = "GPIO227_AH7"; ste,config = <&out_lo>; }; (...) This was tested successfully with the Immersion ISA1200 haptic feedback unit on the Samsung Galaxy S Advance GT-I9070 (Janice) mobile phone. As the CLKOUT clocks need some undefined fixed rate parent clocks that are currently missing from the PRCMU clock implementation, the three simplest are added in this patch: clk38m_to_clkgen, aclk and sysclk. The only parent not yet available in the implementation is clk009, which is a kind of special muxed and divided clock which isn't even implemented in the vendor clock driver. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20220414221751.323525-6-linus.walleij@linaro.org Signed-off-by: Stephen Boyd

clk: ux500: Rewrite PRCMU clocks to use clk_hw_*

2022-04-25T23:17:25Z

This rewrites all the u8500 PRCMU clocks and helper functions to handle clocks using struct clk_hw rather than struct clk, as is normal for modern clock drivers. Use clk_hw_register(), of_clk_add_hw_provider() and stack all the clocks into a compile-time dynamic array of struct clk_hw_onecell_data. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20220414221751.323525-5-linus.walleij@linaro.org Signed-off-by: Stephen Boyd

clk: ux500: Drop .is_prepared state from PRCMU clocks

2022-04-25T23:17:24Z

The core already keeps a software prepare count. Drop this custom software prepare count. The only semantic difference is that if disabling the clock fails, .is_prepared() will still return 1, but this will only serve to confuse the framework, the error message is sufficient. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20220414221751.323525-4-linus.walleij@linaro.org Signed-off-by: Stephen Boyd

clk: ux500: Drop .is_enabled state from PRCMU clocks

2022-04-25T23:17:24Z

The core already keeps a software enable count. Drop this custom software enable count. Reviewed-by: Ulf Hansson Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20220414221751.323525-3-linus.walleij@linaro.org Signed-off-by: Stephen Boyd

clk: ux500: Add driver for the reset portions of PRCC

2021-10-27T01:06:05Z

The Ux500 PRCC (peripheral reset and clock controller) can also control reset of the IP blocks, not just clocks. As the PRCC is probed as a clock controller and we have other platforms implementing combined clock and reset controllers, follow this pattern and implement the PRCC rest controller as part of the clock driver. The reset controller needs to be selected from the machine as Ux500 has traditionally selected its mandatory subsystem prerequisites from there. Cc: Philipp Zabel Cc: Ulf Hansson Signed-off-by: Linus Walleij Link: https://lore.kernel.org/r/20210921184803.1757916-2-linus.walleij@linaro.org Acked-by: Ulf Hansson [sboyd@kernel.org: Dropped allocation error message] Signed-off-by: Stephen Boyd

mfd: db8500-prcmu: Handle missing FW variant

2021-08-09T08:33:29Z

There was an "unknown" firmware variant turning up in the wild causing problems in the clock driver. Add this missing variant and clarify that varian 11 and 15 are Samsung variants, as this is now very well known from released products. Signed-off-by: Linus Walleij Acked-by: Stephen Boyd Signed-off-by: Lee Jones

clk: ux500: Fix up the SGA clock for some variants

2020-01-05T07:27:15Z

Some of the special PRCMU firmware variants were not properly detected in the Ux500 clock driver, resulting in the wrong clock for the SGA. Cc: Ulf Hansson Cc: Stephan Gerhold Signed-off-by: Linus Walleij Link: https://lkml.kernel.org/r/20191217210504.27888-1-linus.walleij@linaro.org Acked-by: Ulf Hansson Reviewed-by: Stephan Gerhold Signed-off-by: Stephen Boyd

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 194

2019-05-30T18:29:22Z

Based on 1 normalized pattern(s): license terms gnu general public license gpl version 2 extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 161 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Reviewed-by: Alexios Zavras Reviewed-by: Steve Winslow Reviewed-by: Richard Fontana Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170027.447718015@linutronix.de Signed-off-by: Greg Kroah-Hartman

clk: ux500: add range to usleep_range

2019-04-11T18:47:50Z

Providing a range for usleep_range() allows the hrtimer subsystem to coalesce timers - the delay is runtime configurable so a factor 2 is taken to provide the range. With the expected range for enable_delay_us being milliseconds, the range should lie in the 250us range which is sufficient for hrtimer optimization. Signed-off-by: Nicholas Mc Guire Acked-by: Ulf Hansson Signed-off-by: Stephen Boyd