linux-dev/drivers/clk/x86, branch master

platform/x86: Drop the PMC_ATOM Kconfig option

2022-06-12T12:41:22Z

The def_bool y PMC_ATOM Kconfig option provides a couple of symbols used by the code enabled by the X86_INTEL_LPSS option and it registers some clocks. These clocks are only registered on Bay Trail, Cherry Trail and Brasswell Intel SoCs and kernels targeting these SoCs must always have the X86_INTEL_LPSS option enabled otherwise many things will not work. Building the PMC_ATOM code on kernels which are not targeting the mentioned SoCs and which do not have the X86_INTEL_LPSS enabled is not useful. This means that we can simplify things by replacing the PMC_ATOM Kconfig option in Makefiles with X86_INTEL_LPSS and then drop the option. Cc: Paul Gortmaker Signed-off-by: Hans de Goede Acked-by: Andy Shevchenko Acked-by: Stephen Boyd Link: https://lore.kernel.org/r/20220503140207.101218-2-hdegoede@redhat.com

clk: x86: Fix clk_gate_flags for RV_CLK_GATE

2022-01-07T01:57:53Z

In newer SoC we have to clear bit for disabling 48MHz oscillator clock gate. Remove CLK_GATE_SET_TO_DISABLE flag for proper enable and disable of 48MHz clock. Signed-off-by: Ajit Kumar Pandey Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/20211212180527.1641362-6-AjitKumar.Pandey@amd.com Signed-off-by: Stephen Boyd

clk: x86: Use dynamic con_id string during clk registration

2022-01-07T01:57:52Z

Replace hard coded con_id string with fch_data->name. We have clk consumers looking up with different clock names, hence use dynamic con_id string during clk lookup registration. fch_data->name will be initialized in acpi driver based on fmw property value. Signed-off-by: Ajit Kumar Pandey Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/20211212180527.1641362-5-AjitKumar.Pandey@amd.com Signed-off-by: Stephen Boyd

x86: clk: clk-fch: Add support for newer family of AMD's SOC

2022-01-07T01:57:52Z

FCH controller clock configuration slightly differs across AMD's SOC architectures. Newer family of SOC only support a 48MHz fix clock while stoney SOC family has a clk_mux to choose 48MHz and 25 MHz clk. At present fixed clk support is only enabled for RV architecture using "is-rv" device property initialized from boot loader. This limit 48MHz fixed clock gate support to RV platform unless we add similar device property in boot loader for other architectures. Add pci_device_id table with Stoney platform id and replace "is-rv" device property check with pci id match to add clk mux support with 25MHz and 48MHz clk support based on clk mux selection. This enable 48Mhz fixed fch clock support by default on all newer SOC's except stoney. Also replace RV with FIXED as a generic naming conventions across all platforms and changed module description. Signed-off-by: Ajit Kumar Pandey Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/20211212180527.1641362-2-AjitKumar.Pandey@amd.com Signed-off-by: Stephen Boyd

clk: x86: Rename clk-lpt to more specific clk-lpss-atom

2021-07-27T21:03:47Z

The LPT stands for Lynxpoint PCH. However the driver is used on a few Intel Atom SoCs. Rename it to reflect this in a way how another clock driver, i.e. clk-pmc-atom, is called. Signed-off-by: Andy Shevchenko Link: https://lore.kernel.org/r/20210722193450.35321-1-andriy.shevchenko@linux.intel.com Acked-by: Rafael J. Wysocki Signed-off-by: Stephen Boyd

Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

2020-08-15T15:18:22Z

Pull more ACPI updates from Rafael Wysocki: "Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk driver and the Designware i2c driver (changes from Akshu Agrawal and Pu Wen)" * tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: clk: x86: Support RV architecture ACPI: APD: Add a fmw property is_raven clk: x86: Change name from ST to FCH ACPI: APD: Change name from ST to FCH i2c: designware: Add device HID for Hygon I2C controller

clk: x86: Support RV architecture

2020-08-07T18:12:00Z

There is minor difference between previous family of SoC and the current one. Which is the there is only 48Mh fixed clk. There is no mux and no option to select another freq as there in previous. Signed-off-by: Akshu Agrawal Reviewed-by: Stephen Boyd Signed-off-by: Rafael J. Wysocki

clk: x86: Change name from ST to FCH

2020-08-07T18:11:59Z

AMD SoC general pupose clk is present in new platforms with minor differences. We can reuse the same clk driver for other platforms. Hence, changing name from ST(SoC) to FCH(IP) Signed-off-by: Akshu Agrawal Reviewed-by: Stephen Boyd Signed-off-by: Rafael J. Wysocki

ACPI: APD: Change name from ST to FCH

2020-08-07T18:11:59Z

AMD SoC general pupose clk is present in new platforms with same MMIO mappings. We can reuse the same clk handler support for other platforms. Hence, changing name from ST(SoC) to FCH(IP) Signed-off-by: Akshu Agrawal Acked-by: Stephen Boyd Signed-off-by: Rafael J. Wysocki

clk: intel: Avoid unnecessary memset by improving code

2020-07-24T08:58:15Z

memset can be avoided in a loop if the variables used are declared inside the loop. Move such variables declaration inside the loop to avoid memset. Signed-off-by: Rahul Tanwar Link: https://lore.kernel.org/r/26624b65d0e6b958c4765a406b9929d1a9ce1c2c.1594880946.git.rahul.tanwar@linux.intel.com [sboyd@kernel.org: Drop NULL assignment that is overwritten] Signed-off-by: Stephen Boyd