linux-dev/drivers/clk/zynqmp, branch linus/master

clk: zynqmp: replace warn_once with pr_debug for failed clock ops

2022-01-25T01:18:23Z

The warning that a clock operation failed is only printed once. However, the function is called for various different clocks. The limit hides the warnings if different clocks are affected by the failures. The clock ops might fail if the firmware that handles the clocks is misconfigured. Therefore, replace the pr_warn_once with pr_debug to allow the user to see all errors if necessary. By default, hide the error messages and let drivers handle the errors. Signed-off-by: Michael Tretter Link: https://lore.kernel.org/r/20220119115434.2042017-1-m.tretter@pengutronix.de Acked-by: Michal Simek Signed-off-by: Stephen Boyd

Merge branches 'clk-kirkwood', 'clk-imx', 'clk-doc', 'clk-zynq' and 'clk-ralink' into clk-next

2021-09-01T22:27:07Z

* clk-kirkwood: clk: kirkwood: Fix a clocking boot regression * clk-imx: clk: imx8mn: Add M7 core clock clk: imx8m: fix clock tree update of TF-A managed clocks clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate clk: imx8mn: use correct mux type for clkout path clk: imx8mm: use correct mux type for clkout path * clk-doc: dt-bindings: clock: samsung: fix header path in example MAINTAINERS: clock: include S3C and S5P in Samsung SoC clock entry dt-bindings: clock: samsung: convert S5Pv210 AudSS to dtschema dt-bindings: clock: samsung: convert Exynos AudSS to dtschema dt-bindings: clock: samsung: convert Exynos4 to dtschema dt-bindings: clock: samsung: convert Exynos3250 to dtschema dt-bindings: clock: samsung: convert Exynos542x to dtschema dt-bindings: clock: samsung: add bindings for Exynos external clock dt-bindings: clock: samsung: convert Exynos5250 to dtschema dt-bindings: clock: brcm,iproc-clocks: fix armpll properties clk: zynqmp: Fix kernel-doc format clk: at91: sama7g5: remove all kernel-doc & kernel-doc warnings clk: zynqmp: fix kernel doc * clk-zynq: clk: zynqmp: Fix a memory leak clk: zynqmp: Check the return type * clk-ralink: clk: ralink: avoid to set 'CLK_IS_CRITICAL' flag for gates

clk: zynqmp: Fix kernel-doc format

2021-08-29T06:43:17Z

Align structure and function names with definitions. Issues are reported by kernel-doc script as: drivers/clk/zynqmp/clk-gate-zynqmp.c:24: warning: expecting prototype for struct clk_gate. Prototype was for struct zynqmp_clk_gate instead drivers/clk/zynqmp/clk-gate-zynqmp.c:75: warning: expecting prototype for zynqmp_clk_gate_is_enable(). Prototype was for zynqmp_clk_gate_is_enabled() instead Signed-off-by: Michal Simek Link: https://lore.kernel.org/r/26526e144296373b2c75e75865dd023158f9bfc7.1629718424.git.michal.simek@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Fix a memory leak

2021-08-29T04:26:12Z

Fix a memory leak of mux. Signed-off-by: Shubhrajyoti Datta Link: https://lore.kernel.org/r/20210818065929.12835-3-shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Check the return type

2021-08-29T04:26:04Z

Currently the return value of of_clk_add_hw_provider is ignored. lets check and return value. Signed-off-by: Shubhrajyoti Datta Link: https://lore.kernel.org/r/20210818065929.12835-2-shubhrajyoti.datta@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: fix kernel doc

2021-08-29T04:19:02Z

Add missing description of 'custom_type_flag' structure member. Fixes: e605fa9c4a0c ("clk: zynqmp: Add support for custom type flags") Signed-off-by: Rajan Vaja Link: https://lore.kernel.org/r/1629720433-19019-1-git-send-email-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Handle divider specific read only flag

2021-06-29T06:35:37Z

Add support for divider specific read only CCF flag (CLK_DIVIDER_READ_ONLY). Signed-off-by: Rajan Vaja Link: https://lore.kernel.org/r/20210628070122.26217-5-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Use firmware specific mux clock flags

2021-06-29T06:35:36Z

Use ZynqMP specific mux clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja Link: https://lore.kernel.org/r/20210628070122.26217-4-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Use firmware specific divider clock flags

2021-06-29T06:35:36Z

Use ZynqMP specific divider clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja Link: https://lore.kernel.org/r/20210628070122.26217-3-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd

clk: zynqmp: Use firmware specific common clock flags

2021-06-29T06:35:36Z

Currently firmware passes CCF specific flags to ZynqMP clock driver. So firmware needs to be updated if CCF flags are changed. The firmware should have its own 'flag number space' that is distinct from the common clk framework's 'flag number space'. So define and use ZynqMP specific common clock flags instead of using CCF flags. Signed-off-by: Rajan Vaja Link: https://lore.kernel.org/r/20210628070122.26217-2-rajan.vaja@xilinx.com Signed-off-by: Stephen Boyd