<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/crypto/hisilicon/sec2, branch linus/master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/crypto/hisilicon/sec2?h=linus%2Fmaster</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/crypto/hisilicon/sec2?h=linus%2Fmaster'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-05-20T05:54:45Z</updated>
<entry>
<title>crypto: hisilicon/sec - delete the flag CRYPTO_ALG_ALLOCATES_MEMORY</title>
<updated>2022-05-20T05:54:45Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2022-05-13T08:02:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=2d33f5771b513f7dfb819563d4b38b687f2a4982'/>
<id>urn:sha1:2d33f5771b513f7dfb819563d4b38b687f2a4982</id>
<content type='text'>
Should not to uses the CRYPTO_ALG_ALLOCATES_MEMORY in SEC2. The SEC2
driver uses the pre-allocated buffers, including the src sgl pool, dst
sgl pool and other qp ctx resources. (e.g. IV buffer, mac buffer, key
buffer). The SEC2 driver doesn't allocate memory during request processing.
The driver only maps software sgl to allocated hardware sgl during I/O. So
here is fix it.

Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec - support last word dumping</title>
<updated>2022-04-15T08:34:29Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2022-04-09T08:03:26Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8a88d0914529f3558bb160cb862ef4daafebb7b4'/>
<id>urn:sha1:8a88d0914529f3558bb160cb862ef4daafebb7b4</id>
<content type='text'>
Add last word dumping function during sec engine controller reset.

Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec - support register checking</title>
<updated>2022-04-15T08:34:28Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2022-04-09T08:03:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=16175030bb5b53ab125480af6cfb73ae8064d780'/>
<id>urn:sha1:16175030bb5b53ab125480af6cfb73ae8064d780</id>
<content type='text'>
The value of the register is changed after the task running. A debugfs
file node is added to help users to check the change of register values.

Signed-off-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>Merge tag 'vfio-v5.18-rc1' of https://github.com/awilliam/linux-vfio</title>
<updated>2022-03-24T19:35:59Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2022-03-24T19:35:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=7403e6d8263937dea206dd201fed1ceed190ca18'/>
<id>urn:sha1:7403e6d8263937dea206dd201fed1ceed190ca18</id>
<content type='text'>
Pull VFIO updates from Alex Williamson:

 - Introduce new device migration uAPI and implement device specific
   mlx5 vfio-pci variant driver supporting new protocol (Jason
   Gunthorpe, Yishai Hadas, Leon Romanovsky)

 - New HiSilicon acc vfio-pci variant driver, also supporting migration
   interface (Shameer Kolothum, Longfang Liu)

 - D3hot fixes for vfio-pci-core (Abhishek Sahu)

 - Document new vfio-pci variant driver acceptance criteria
   (Alex Williamson)

 - Fix UML build unresolved ioport_{un}map() functions
   (Alex Williamson)

 - Fix MAINTAINERS due to header movement (Lukas Bulwahn)

* tag 'vfio-v5.18-rc1' of https://github.com/awilliam/linux-vfio: (31 commits)
  vfio-pci: Provide reviewers and acceptance criteria for variant drivers
  MAINTAINERS: adjust entry for header movement in hisilicon qm driver
  hisi_acc_vfio_pci: Use its own PCI reset_done error handler
  hisi_acc_vfio_pci: Add support for VFIO live migration
  crypto: hisilicon/qm: Set the VF QM state register
  hisi_acc_vfio_pci: Add helper to retrieve the struct pci_driver
  hisi_acc_vfio_pci: Restrict access to VF dev BAR2 migration region
  hisi_acc_vfio_pci: add new vfio_pci driver for HiSilicon ACC devices
  hisi_acc_qm: Move VF PCI device IDs to common header
  crypto: hisilicon/qm: Move few definitions to common header
  crypto: hisilicon/qm: Move the QM header to include/linux
  vfio/mlx5: Fix to not use 0 as NULL pointer
  PCI/IOV: Fix wrong kernel-doc identifier
  vfio/mlx5: Use its own PCI reset_done error handler
  vfio/pci: Expose vfio_pci_core_aer_err_detected()
  vfio/mlx5: Implement vfio_pci driver for mlx5 devices
  vfio/mlx5: Expose migration commands over mlx5 device
  vfio: Remove migration protocol v1 documentation
  vfio: Extend the device migration protocol with RUNNING_P2P
  vfio: Define device migration protocol v2
  ...
</content>
</entry>
<entry>
<title>hisi_acc_vfio_pci: Add helper to retrieve the struct pci_driver</title>
<updated>2022-03-15T17:34:09Z</updated>
<author>
<name>Shameer Kolothum</name>
<email>shameerali.kolothum.thodi@huawei.com</email>
</author>
<published>2022-03-08T18:48:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=442fbc099b839551f8576723da22c1269cc695ce'/>
<id>urn:sha1:442fbc099b839551f8576723da22c1269cc695ce</id>
<content type='text'>
struct pci_driver pointer is an input into the pci_iov_get_pf_drvdata().
Introduce helpers to retrieve the ACC PF dev struct pci_driver pointers
as we use this in ACC vfio migration driver.

Acked-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Acked-by: Kai Ye &lt;yekai13@huawei.com&gt;
Acked-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Signed-off-by: Shameer Kolothum &lt;shameerali.kolothum.thodi@huawei.com&gt;
Link: https://lore.kernel.org/r/20220308184902.2242-7-shameerali.kolothum.thodi@huawei.com
Signed-off-by: Alex Williamson &lt;alex.williamson@redhat.com&gt;
</content>
</entry>
<entry>
<title>hisi_acc_qm: Move VF PCI device IDs to common header</title>
<updated>2022-03-15T17:34:08Z</updated>
<author>
<name>Shameer Kolothum</name>
<email>shameerali.kolothum.thodi@huawei.com</email>
</author>
<published>2022-03-08T18:48:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=fae74feacd2dfb6172c4862fc760f969a991c06f'/>
<id>urn:sha1:fae74feacd2dfb6172c4862fc760f969a991c06f</id>
<content type='text'>
Move the PCI Device IDs of HiSilicon ACC VF devices to a common header
and also use a uniform naming convention.

This will be useful when we introduce the vfio PCI HiSilicon ACC live
migration driver in subsequent patches.

Cc: Bjorn Helgaas &lt;bhelgaas@google.com&gt;
Acked-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Acked-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Acked-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Shameer Kolothum &lt;shameerali.kolothum.thodi@huawei.com&gt;
Acked-by: Bjorn Helgaas &lt;bhelgaas@google.com&gt;	# pci_ids.h
Link: https://lore.kernel.org/r/20220308184902.2242-4-shameerali.kolothum.thodi@huawei.com
Signed-off-by: Alex Williamson &lt;alex.williamson@redhat.com&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm: Move the QM header to include/linux</title>
<updated>2022-03-15T17:34:08Z</updated>
<author>
<name>Shameer Kolothum</name>
<email>shameerali.kolothum.thodi@huawei.com</email>
</author>
<published>2022-03-08T18:48:54Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=ff5812e00d5e7bdeae68784d99686eff67896931'/>
<id>urn:sha1:ff5812e00d5e7bdeae68784d99686eff67896931</id>
<content type='text'>
Since we are going to introduce VFIO PCI HiSilicon ACC driver for live
migration in subsequent patches, move the ACC QM header file to a
common include dir.

Acked-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Acked-by: Longfang Liu &lt;liulongfang@huawei.com&gt;
Acked-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Shameer Kolothum &lt;shameerali.kolothum.thodi@huawei.com&gt;
Link: https://lore.kernel.org/r/20220308184902.2242-2-shameerali.kolothum.thodi@huawei.com
Signed-off-by: Alex Williamson &lt;alex.williamson@redhat.com&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec - fix the aead software fallback for engine</title>
<updated>2022-02-23T03:28:33Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2022-02-19T08:08:08Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=0a2a464f863187f97e96ebc6384c052cafd4a54c'/>
<id>urn:sha1:0a2a464f863187f97e96ebc6384c052cafd4a54c</id>
<content type='text'>
Due to the subreq pointer misuse the private context memory. The aead
soft crypto occasionally casues the OS panic as setting the 64K page.
Here is fix it.

Fixes: 6c46a3297bea ("crypto: hisilicon/sec - add fallback tfm...")
Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec - not need to enable sm4 extra mode at HW V3</title>
<updated>2022-02-18T05:21:10Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2022-02-11T09:08:18Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f8a2652826444d13181061840b96a5d975d5b6c6'/>
<id>urn:sha1:f8a2652826444d13181061840b96a5d975d5b6c6</id>
<content type='text'>
It is not need to enable sm4 extra mode in at HW V3. Here is fix it.

Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec - add the register configuration for HW V3</title>
<updated>2022-02-18T05:21:10Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2022-02-11T09:07:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=aec01cc8d119b453b26da9ba45ec60ac2b395e18'/>
<id>urn:sha1:aec01cc8d119b453b26da9ba45ec60ac2b395e18</id>
<content type='text'>
Added the register configuration of the SVA mode for HW V3.

Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
