<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/crypto/hisilicon, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/crypto/hisilicon?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/crypto/hisilicon?h=master'/>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/'/>
<updated>2022-09-24T08:14:44Z</updated>
<entry>
<title>crypto: hisilicon/qm - fix the qos value initialization</title>
<updated>2022-09-24T08:14:44Z</updated>
<author>
<name>Kai Ye</name>
<email>yekai13@huawei.com</email>
</author>
<published>2022-09-17T10:03:45Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f5b657e5dbf830cfcb19b588b784b8190a5164a0'/>
<id>urn:sha1:f5b657e5dbf830cfcb19b588b784b8190a5164a0</id>
<content type='text'>
The default qos value is not initialized when sriov is repeatedly enabled
and disabled. So add the vf qos value initialized in the sriov enable
process.

Signed-off-by: Kai Ye &lt;yekai13@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon - support get algs by the capability register</title>
<updated>2022-09-16T10:29:46Z</updated>
<author>
<name>Zhiqi Song</name>
<email>songzhiqi1@huawei.com</email>
</author>
<published>2022-09-09T09:47:04Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d310dc2554a5296a338f974d2b4e4f9af2687558'/>
<id>urn:sha1:d310dc2554a5296a338f974d2b4e4f9af2687558</id>
<content type='text'>
The value of qm algorithm can change dynamically according to the
value of the capability register.

Add xxx_set_qm_algs() function to obtain the algs that the
hardware device supported from the capability register and set
them into usr mode attribute files.

Signed-off-by: Zhiqi Song &lt;songzhiqi1@huawei.com&gt;
Signed-off-by: Wenkai Lin &lt;linwenkai6@hisilicon.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/sec - get algorithm bitmap from registers</title>
<updated>2022-09-16T10:29:45Z</updated>
<author>
<name>Wenkai Lin</name>
<email>linwenkai6@hisilicon.com</email>
</author>
<published>2022-09-09T09:47:03Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=921715b6b7827157bba6e8153d7a09774b0d034f'/>
<id>urn:sha1:921715b6b7827157bba6e8153d7a09774b0d034f</id>
<content type='text'>
Add function 'sec_get_alg_bitmap' to get hardware algorithm bitmap
before register algorithm to crypto, instead of determining
whether to register an algorithm based on hardware platform's version.

Signed-off-by: Wenkai Lin &lt;linwenkai6@hisilicon.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/zip - support zip capability</title>
<updated>2022-09-16T10:29:45Z</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2022-09-09T09:47:02Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=db700974b69d2c12a8fe84c45820892416a1e265'/>
<id>urn:sha1:db700974b69d2c12a8fe84c45820892416a1e265</id>
<content type='text'>
Add function 'hisi_zip_alg_support' to get device configuration
information from capability registers, instead of determining whether
to register an algorithm based on hardware platform's version.

Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/hpre - optimize registration of ecdh</title>
<updated>2022-09-16T10:29:45Z</updated>
<author>
<name>Zhiqi Song</name>
<email>songzhiqi1@huawei.com</email>
</author>
<published>2022-09-09T09:47:01Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b1be70a8c983a5bd12d88181b75d0f550086cb44'/>
<id>urn:sha1:b1be70a8c983a5bd12d88181b75d0f550086cb44</id>
<content type='text'>
Use table to store the different ecdh curve configuration,
making the registration of ecdh clearer and expansion more
convenient.

Signed-off-by: Zhiqi Song &lt;songzhiqi1@huawei.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/hpre - support hpre capability</title>
<updated>2022-09-16T10:29:45Z</updated>
<author>
<name>Zhiqi Song</name>
<email>songzhiqi1@huawei.com</email>
</author>
<published>2022-09-09T09:47:00Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=f214d59a0603543cfa7c6c1cf2eb130ac77480c3'/>
<id>urn:sha1:f214d59a0603543cfa7c6c1cf2eb130ac77480c3</id>
<content type='text'>
Read some hpre device configuration info from capability
register, instead of fixed macros.

Signed-off-by: Zhiqi Song &lt;songzhiqi1@huawei.com&gt;
Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm - support get device irq information from hardware registers</title>
<updated>2022-09-16T10:29:45Z</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2022-09-09T09:46:59Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=3536cc55cadaf2a03241915f9cfdaf6cd073e4fe'/>
<id>urn:sha1:3536cc55cadaf2a03241915f9cfdaf6cd073e4fe</id>
<content type='text'>
Support get device irq information from hardware registers
instead of fixed macros.

Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm - get error type from hardware registers</title>
<updated>2022-09-16T10:29:45Z</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2022-09-09T09:46:58Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=d90fab0deb8e580aa001f6876e4436c21e944f27'/>
<id>urn:sha1:d90fab0deb8e580aa001f6876e4436c21e944f27</id>
<content type='text'>
Hardware V3 and later versions support get error type from
registers. To be compatible with later hardware versions,
get error type from registers instead of fixed marco.

Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm - add UACCE_CMD_QM_SET_QP_INFO support</title>
<updated>2022-09-16T10:29:44Z</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2022-09-09T09:46:57Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c832da79cbf9448e7ece097c3a93996b4c74a83e'/>
<id>urn:sha1:c832da79cbf9448e7ece097c3a93996b4c74a83e</id>
<content type='text'>
To be compatible with accelerator devices of different
versions, 'UACCE_CMD_QM_SET_QP_INFO' ioctl is added to obtain
queue information in userspace, including queue depth and buffer
description size.

Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: hisilicon/qm - get qp num and depth from hardware registers</title>
<updated>2022-09-16T10:29:44Z</updated>
<author>
<name>Weili Qian</name>
<email>qianweili@huawei.com</email>
</author>
<published>2022-09-09T09:46:56Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=129a9f340172b4f3857260a7a7bb9d7b3496ba50'/>
<id>urn:sha1:129a9f340172b4f3857260a7a7bb9d7b3496ba50</id>
<content type='text'>
Hardware V3 and later versions can obtain qp num and depth supported
by the hardware from registers. To be compatible with later hardware
versions, get qp num and depth from registers instead of fixed marcos.

Signed-off-by: Weili Qian &lt;qianweili@huawei.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
