<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-dev/drivers/crypto/qat/qat_common/Makefile, branch master</title>
<subtitle>Linux kernel development work - see feature branches</subtitle>
<id>https://git.zx2c4.com/linux-dev/atom/drivers/crypto/qat/qat_common/Makefile?h=master</id>
<link rel='self' href='https://git.zx2c4.com/linux-dev/atom/drivers/crypto/qat/qat_common/Makefile?h=master'/>
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<updated>2022-07-08T07:15:59Z</updated>
<entry>
<title>crypto: qat - expose device state through sysfs for 4xxx</title>
<updated>2022-07-08T07:15:59Z</updated>
<author>
<name>Giovanni Cabiddu</name>
<email>giovanni.cabiddu@intel.com</email>
</author>
<published>2022-06-27T08:36:49Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=5ee52118ac1481dd8a8f7e6a9bfe6ee05ac6ec92'/>
<id>urn:sha1:5ee52118ac1481dd8a8f7e6a9bfe6ee05ac6ec92</id>
<content type='text'>
Expose the device state through an attribute in sysfs and allow to
change it. This is to stop and shutdown a QAT device in order to change
its configuration.

The state attribute has been added to a newly created `qat` attribute
group which will contain all _QAT specific_ attributes.

The logic that implements the sysfs entries is part of a new file,
adf_sysfs.c. This exposes an entry point to allow the driver to create
attributes.

The function that creates the sysfs attributes is called from the probe
function of the driver and not in the state machine init function to
allow the change of states even if the device is in the down state.

In order to restore the device configuration between a transition from
down to up, the function that configures the devices has been abstracted
into the HW data structure.

The `state` attribute is only exposed for qat_4xxx devices.

Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Co-developed-by: Tomasz Kowallik &lt;tomaszx.kowalik@intel.com&gt;
Signed-off-by: Tomasz Kowallik &lt;tomaszx.kowalik@intel.com&gt;
Reviewed-by: Adam Guerin &lt;adam.guerin@intel.com&gt;
Reviewed-by: Fiona Trahe &lt;fiona.trahe@intel.com&gt;
Reviewed-by: Wojciech Ziemba &lt;wojciech.ziemba@intel.com&gt;
Reviewed-by: Vladis Dronov &lt;vdronov@redhat.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - refactor submission logic</title>
<updated>2022-05-20T05:49:17Z</updated>
<author>
<name>Giovanni Cabiddu</name>
<email>giovanni.cabiddu@intel.com</email>
</author>
<published>2022-05-09T13:34:09Z</published>
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<id>urn:sha1:af88d3c109aa5edfaa11c9a26d9c0ff21ddf501c</id>
<content type='text'>
All the algorithms in qat_algs.c and qat_asym_algs.c use the same
pattern to submit messages to the HW queues. Move the submission loop
to a new function, qat_alg_send_message(), and share it between the
symmetric and the asymmetric algorithms.

As part of this rework, since the number of retries before returning an
error is inconsistent between the symmetric and asymmetric
implementations, set it to a value that works for both (i.e. 20, was 10
in qat_algs.c and 100 in qat_asym_algs.c)

In addition fix the return code reported when the HW queues are full.
In that case return -ENOSPC instead of -EBUSY.

Including stable in CC since (1) the error code returned if the HW queues
are full is incorrect and (2) to facilitate the backport of the next fix
"crypto: qat - add backlog mechanism".

Cc: stable@vger.kernel.org
Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Reviewed-by: Marco Chiappero &lt;marco.chiappero@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - enable power management for QAT GEN4</title>
<updated>2022-02-18T05:21:09Z</updated>
<author>
<name>Wojciech Ziemba</name>
<email>wojciech.ziemba@intel.com</email>
</author>
<published>2022-02-10T13:38:27Z</published>
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<id>urn:sha1:e5745f34113b758b45d134dec04a7df94dc67131</id>
<content type='text'>
Add support for HW QAT Power Management (PM) feature.
This feature is enabled at init time (1) by sending an admin message to
the firmware, targeting the admin AE, that sets the idle time before
the device changes state and (2) by unmasking the PM source of interrupt
in ERRMSK2.

The interrupt handler is extended to handle a PM interrupt which
is triggered by HW when a PM transition occurs. In this case, the
driver responds acknowledging the transaction using the HOST_MSG
mailbox.

Signed-off-by: Wojciech Ziemba &lt;wojciech.ziemba@intel.com&gt;
Co-developed-by: Marcinx Malinowski &lt;marcinx.malinowski@intel.com&gt;
Signed-off-by: Marcinx Malinowski &lt;marcinx.malinowski@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Reviewed-by: Marco Chiappero &lt;marco.chiappero@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - add PFVF support to the GEN4 host driver</title>
<updated>2021-12-24T03:18:27Z</updated>
<author>
<name>Marco Chiappero</name>
<email>marco.chiappero@intel.com</email>
</author>
<published>2021-12-16T09:13:31Z</published>
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<id>urn:sha1:a9dc0d966605377e9aa512efdcaf9653f40cc2d5</id>
<content type='text'>
So far PFVF support for GEN4 devices has been kept effectively disabled
due to lack of support. This patch adds all the GEN4 specific logic to
make PFVF fully functional on PF.

Signed-off-by: Marco Chiappero &lt;marco.chiappero@intel.com&gt;
Co-developed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Reviewed-by: Fiona Trahe &lt;fiona.trahe@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - abstract PFVF messages with struct pfvf_message</title>
<updated>2021-12-24T03:18:25Z</updated>
<author>
<name>Marco Chiappero</name>
<email>marco.chiappero@intel.com</email>
</author>
<published>2021-12-16T09:13:20Z</published>
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<id>urn:sha1:db1c034801c402b1f600ef7f753494479950f78e</id>
<content type='text'>
This implementation of the PFVF protocol was designed around the GEN2
devices and its CSR format. In order to support future generations,
which come with differently sized fields, change the definition of the PFVF
message and make it abstract by means of a new pfvf_message struct. Also,
introduce some utilities to translate to and from the new message format
and the device specific CSR format.

Signed-off-by: Marco Chiappero &lt;marco.chiappero@intel.com&gt;
Reviewed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Reviewed-by: Fiona Trahe &lt;fiona.trahe@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - reorganize PFVF code</title>
<updated>2021-11-26T05:20:47Z</updated>
<author>
<name>Marco Chiappero</name>
<email>marco.chiappero@intel.com</email>
</author>
<published>2021-11-17T14:30:51Z</published>
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<id>urn:sha1:09ce899a592f7a8ee19857ad0ef394e31be83c1d</id>
<content type='text'>
Reorganize the structure of the PFVF code by moving the content of
adf_pf2vf_msg.c and adf_vf2pf_msg.c.

The logic that handles high level messages has been moved to
adf_pfvf_pf_msg.c and adf_pfvf_vf_msg.c.
The implementation of low level communication primitives and the
protocol is now included in adf_pfvf_pf_proto.c and adf_pfvf_vf_proto.c.

In addition, the file adf_pf2vf_msg.h has been renamed in adf_pfvf_msg.h
since it common to PF and VF and the copyright date for the touched
files has been updated.

Signed-off-by: Marco Chiappero &lt;marco.chiappero@intel.com&gt;
Co-developed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - add pfvf_ops</title>
<updated>2021-11-26T05:20:46Z</updated>
<author>
<name>Marco Chiappero</name>
<email>marco.chiappero@intel.com</email>
</author>
<published>2021-11-17T14:30:47Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=bc63dabe525402b91320192ff1758f0d05b159c6'/>
<id>urn:sha1:bc63dabe525402b91320192ff1758f0d05b159c6</id>
<content type='text'>
Add pfvf_ops structure to isolate PFVF related functions inside the
adf_hw_device_data structure.

For GEN2, the structure is populated using one of the two helper
functions, adf_gen2_init_pf_pfvf_ops() or adf_gen2_init_vf_pfvf_ops(),
for the PF and VF driver respectively.

For the DH895XCC PF driver, the structure is populated using
adf_gen2_init_pf_pfvf_ops() but some of the functions are then
overwritten.

Signed-off-by: Marco Chiappero &lt;marco.chiappero@intel.com&gt;
Co-developed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - relocate PFVF PF related logic</title>
<updated>2021-11-26T05:20:46Z</updated>
<author>
<name>Marco Chiappero</name>
<email>marco.chiappero@intel.com</email>
</author>
<published>2021-11-17T14:30:44Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=b85bd9457dc302749411a9b43f78fd493499f3ef'/>
<id>urn:sha1:b85bd9457dc302749411a9b43f78fd493499f3ef</id>
<content type='text'>
Move device specific PFVF logic related to the PF to the newly created
adf_gen2_pfvf.c.
This refactory is done to isolate the GEN2 PFVF code into its own file
in preparation for the introduction of support for PFVF for GEN4
devices.

In addition the PFVF PF logic for dh895xcc has been isolated to
adf_dh895xcc_hw_data.c.

Signed-off-by: Marco Chiappero &lt;marco.chiappero@intel.com&gt;
Co-developed-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - add qat_4xxx driver</title>
<updated>2020-11-20T03:45:34Z</updated>
<author>
<name>Giovanni Cabiddu</name>
<email>giovanni.cabiddu@intel.com</email>
</author>
<published>2020-11-13T16:46:43Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=8c8268166e83425243789c5781c92e7fa33b703b'/>
<id>urn:sha1:8c8268166e83425243789c5781c92e7fa33b703b</id>
<content type='text'>
Add support for QAT 4xxx devices.

Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Reviewed-by: Fiona Trahe &lt;fiona.trahe@intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
<entry>
<title>crypto: qat - fix configuration of iov threads</title>
<updated>2020-10-30T06:34:47Z</updated>
<author>
<name>Giovanni Cabiddu</name>
<email>giovanni.cabiddu@intel.com</email>
</author>
<published>2020-10-12T20:38:20Z</published>
<link rel='alternate' type='text/html' href='https://git.zx2c4.com/linux-dev/commit/?id=c4e8428673425c5b0c7280387c5cb35d60959b97'/>
<id>urn:sha1:c4e8428673425c5b0c7280387c5cb35d60959b97</id>
<content type='text'>
The number of AE2FUNC_MAP registers is different in every QAT device
(c62x, c3xxx and dh895xcc) although the logic and the register offsets
are the same across devices.

This patch separates the logic that configures the iov threads in a
common function that takes as input the number of AE2FUNC_MAP registers
supported by a device. The function is then added to the
adf_hw_device_data structure of each device, and called with the
appropriate parameters.

The configure iov thread logic is added to a new file,
adf_gen2_hw_data.c, that is going to contain code that is shared across
QAT GEN2 devices.

Signed-off-by: Giovanni Cabiddu &lt;giovanni.cabiddu@intel.com&gt;
Reviewed-by: Fiona Trahe &lt;fiona.trahe@intel.com&gt;
Reviewed-by: Wojciech Ziemba &lt;wojciech.ziemba@intel.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Herbert Xu &lt;herbert@gondor.apana.org.au&gt;
</content>
</entry>
</feed>
